Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-03-08
2005-03-08
Sarkar, Asok Kumar (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S199000, C438S587000
Reexamination Certificate
active
06864163
ABSTRACT:
For fabricating dual gate structures of complementary field effect transistors, a gate material is deposited into an opening disposed over a P-well and an N-well having the complementary field effect transistors formed therein. A portion of the gate material disposed over one of the P-well or the N-well is modified to form a first gate structure, and the remaining gate material over the other one of the P-well or the N-well forms a second gate structure. The first and second gate structures form the dual gate structures of the complementary field effect transistors.
REFERENCES:
patent: 4808261 (1989-02-01), Ghidini et al.
patent: 6130123 (2000-10-01), Liang et al.
patent: 6444512 (2002-09-01), Madhukar et al.
patent: 20040080001 (2004-04-01), Takeuchi
Pan James
Yu Allen S.
Advanced Micro Devices , Inc.
Choi Monica H.
Sarkar Asok Kumar
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