Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-03-15
2005-03-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S200000, C438S231000, C438S250000, C438S278000, C438S304000
Reexamination Certificate
active
06867103
ABSTRACT:
A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer and a buried oxide layer. The doped silicon layer has a first conductivity type and overlies the buried oxide layer. Ions are implanted into the SOI substrate to form higher concentration regions in the doped silicon layer. The higher concentration regions have the first conductivity type and are formed substantially below the top surface of the doped silicon layer. MOS gates are formed. These MOS gates include an electrode layer overlying the doped silicon layer with a gate oxide layer therebetween. Source and drain regions are formed in the doped silicon layer to complete the transistors in the manufacture of the integrated circuit device. The source and drain regions contact the higher concentration regions and have a second conductivity type.
REFERENCES:
patent: 5571738 (1996-11-01), Krivokapic
patent: 5759901 (1998-06-01), Loh et al.
patent: 5773348 (1998-06-01), Wu
patent: 5976921 (1999-11-01), Maeda
patent: 5982003 (1999-11-01), Hu et al.
patent: 6034397 (2000-03-01), Voldman
patent: 6034399 (2000-03-01), Brady et al.
patent: 6057184 (2000-05-01), Brown et al.
patent: 6133078 (2000-10-01), Yun
patent: 6137141 (2000-10-01), Son et al.
patent: 6143594 (2000-11-01), Tsao et al.
patent: 6222710 (2001-04-01), Yamaguchi
patent: 6242763 (2001-06-01), Chen et al.
patent: 6297082 (2001-10-01), Lin et al.
patent: 6355962 (2002-03-01), Liang et al.
patent: 6383876 (2002-05-01), Son et al.
patent: 6420761 (2002-07-01), Gauthier, Jr. et al.
patent: 6429482 (2002-08-01), Culp et al.
patent: 6452236 (2002-09-01), Nadakumar et al.
patent: 6465307 (2002-10-01), Chidambaram et al.
patent: 6475838 (2002-11-01), Bryant et al.
patent: 6482703 (2002-11-01), Yu
patent: 6514839 (2003-02-01), Ker et al.
patent: 6642581 (2003-11-01), Matsuda et al.
patent: 20020028546 (2002-03-01), Shin et al.
patent: 20020033511 (2002-03-01), Babcock et al.
patent: 20020109187 (2002-08-01), Matsumoto et al.
patent: 20020167050 (2002-11-01), Brown et al.
patent: 20020185678 (2002-12-01), Kim
patent: 20030137789 (2003-07-01), Walker et al.
patent: 20030235936 (2003-12-01), Snyder et al.
Rocchegiani Renzo N
Smith Matthew
Taiwan Semiconductor Manufacturing Company
Thomas Kayden Horstemeyer & Risley
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