Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-01-04
2005-01-04
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S316000, C438S197000
Reexamination Certificate
active
06838346
ABSTRACT:
A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxal layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used o interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
REFERENCES:
patent: 4343015 (1982-08-01), Baliga
patent: 4531173 (1985-07-01), Yamada
patent: 4626789 (1986-12-01), Nakata et al.
patent: 4626879 (1986-12-01), Colak
patent: 4738936 (1988-04-01), Rice
patent: 4811075 (1989-03-01), Eklund
patent: 4890144 (1989-12-01), Teng et al.
patent: 4890146 (1989-12-01), Williams
patent: 4929987 (1990-05-01), Einthoven
patent: 5068700 (1991-11-01), Yamaguchi et al.
patent: 5146298 (1992-09-01), Eklund
patent: 5155574 (1992-10-01), Yamaguchi
patent: 5237193 (1993-08-01), Williams et al.
patent: 5258636 (1993-11-01), Rumennik et al.
patent: 5306656 (1994-04-01), Williams et al.
patent: 5313082 (1994-05-01), Eklund
patent: 5368136 (1994-11-01), Williams et al.
patent: 5514608 (1996-05-01), Williams et al.
patent: 5637898 (1997-06-01), Baliga
patent: 5665994 (1997-09-01), Palara
patent: 5760440 (1998-06-01), Kitamura et al.
patent: 5821144 (1998-10-01), D'Anna et al.
patent: 5869875 (1999-02-01), Hebert
patent: 5917216 (1999-06-01), Floyd et al.
patent: 5973360 (1999-10-01), Tihanyi
patent: 5998833 (1999-12-01), Baliga
patent: 6049108 (2000-04-01), Williams et al.
patent: 6127703 (2000-10-01), Letavic et al.
patent: 6184555 (2001-02-01), Tihanyi et al.
patent: 6191447 (2001-02-01), Baliga
patent: 6194283 (2001-02-01), Gardner et al.
patent: 6207994 (2001-03-01), Rumennik et al.
patent: 6294818 (2001-09-01), Fujihira
patent: 6353252 (2002-03-01), Yasuhara et al.
patent: 6365932 (2002-04-01), Kouno et al.
patent: 6388286 (2002-05-01), Baliga
patent: 6462377 (2002-10-01), Hurky et al.
patent: 6468847 (2002-10-01), Disney
patent: 6509220 (2003-01-01), Disney
patent: 6525372 (2003-02-01), Baliga
patent: 6555873 (2003-04-01), Disney et al.
patent: 6573558 (2003-06-01), Disney
patent: 6635544 (2003-10-01), Disney
patent: 6667213 (2003-12-01), Disney
patent: 20010015459 (2001-08-01), Watanabe et al.
patent: 20020056884 (2002-05-01), Baliga
patent: 20020175351 (2002-11-01), Baliga
patent: 43 09 764 (1994-09-01), None
patent: 1073 123 (2000-07-01), None
patent: 2 309 336 (1997-01-01), None
patent: 56-38867 (1981-04-01), None
patent: 57-10975 (1982-01-01), None
patent: 57-12557 (1982-01-01), None
patent: 57-12558 (1982-01-01), None
patent: 60-64471 (1985-04-01), None
patent: 3-211771 (1991-09-01), None
patent: 4107877 (1992-04-01), None
patent: 04-107867 (1994-08-01), None
patent: 6-224426 (1994-08-01), None
patent: 2000-349288 (2000-12-01), None
patent: WO 97 35346 (1997-11-01), None
patent: WO 99/34449 (1999-07-01), None
patent: WO 00 33385 (2000-06-01), None
patent: WO 02 41402 (2002-05-01), None
patent: WO 02 099909 (2002-12-01), None
International Electron Device Meeting 1979—Washington, D.C., Dec. 3-4-5, Sponsored by Electron Devices Society of IEEE, pp. 238-241.
“Realization of High Breakdown Voltage (>700V) in Thin SOI Devices” S. Menchant, et al., Phillips Laboratories North American Phillips Corportation 1991 IEEE, pp. 31-35.
“Theory of Semiconductor Superjunction Devices,” Fujihira, Japan Journal of Applied Physics Part 1, Oct. 1997, vol. 36, No. 10, pp. 6254-6262.
“Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance,” B. Shieh, K.C. Sanaswat IEEE Electron Device Hettas, vol. 19, No. 1, Jan. 1998.
“Oxide-Bypassed VDMOS (OBVDMOS): An Alternative to Superjunction High-Voltage MOS Power Devices,” Yung C. Liang, et al., Aug. 2001, IEEE Electron Device Letters vol. 22, No. 8, pp. 407-409.
“Comparison of High-Voltage Devices for Power Integrated Circuits,” R. Jay Anaman, et al., IEDM 84, pp. 258-261.
“A New Generation of High-Voltage MOSFET's Breaks the Limit Line of Silicon,” G. Debby, et al., Siemens AG, Semiconductor Division, Munchen, Germany; IEDM 98-683 to IEDM 98-685.
“High Performance 600V Smart Power Technology Based on Thin Layer Silicon-on-Insulator,” T. Levatic, et al., Philips Research, Philips Electronics North America Corporation, 4 Pages.
“Modern Semiconductor Device Physics,” S.M. Sze, John Wiley & Sons, Chapter 4 (“Power Devices”) pp. 203-206, (1998).
“Modeling Optimization of Lateral High-Voltage IC Devices to Minimize 3-D Effects,” Hamza Yilmaz, R&D Engineering, Semiconductor Business Division, General Electric Company, NC, pp. 290-297.
“Optimization of the Specific On-Resistance of the COOLMOS™,” Chen, et al., IEEE Transactions on Electronic Devices, vol. 48, No. 2, Feb. 2001.
“Lateral Unbalanced Super Junction (USJ) / 3D-RESURF for High Breakdown Voltage on SOI,” Ng, et al., pp. 395-398, Apr. 6, 2001.
“Static and Dynamic Electricity,” William R. Smythe, McGraw-Hill Book Company, Inc., New York, 1950.
Burgess & Bereznak LLP
Nhu David
Power Integrations, Inc.
LandOfFree
Method of fabricating a high-voltage transistor with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a high-voltage transistor with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a high-voltage transistor with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3377488