Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2005-01-18
2005-01-18
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S401000, C713S500000, C713S503000, C711S100000, C711S105000, C327S147000, C327S149000, C327S157000, C327S158000, C327S161000
Reexamination Certificate
active
06845459
ABSTRACT:
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.
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Browne Lynne H.
Micro)n Technology, Inc.
Patel Nitin C.
Thorp Reed & Armstrong LLP
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