Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-03-01
2005-03-01
Gurley, Lynne A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S243000, C438S246000, C438S294000, C438S295000, C438S296000, C438S359000, C438S360000, C438S361000, C438S391000, C438S397000, C438S424000, C438S427000, C438S429000, C438S430000, C438S431000, C438S432000
Reexamination Certificate
active
06861311
ABSTRACT:
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate. Conductive material is formed which is received within at least one of the isolation regions. In one preferred implementation, a silicon-on-insulator (SOI) substrate is utilized to support integrated circuitry which is formed utilizing the methodical aspects of the invention. In another preferred implementation, other substrates, such as conventional bulk substrates are utilized.
REFERENCES:
patent: 4604162 (1986-08-01), Sobczak
patent: 4700461 (1987-10-01), Choi et al.
patent: 5011783 (1991-04-01), Ogawa et al.
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5241211 (1993-08-01), Tashiro
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5539229 (1996-07-01), Noble, Jr et al.
patent: 5599724 (1997-02-01), Yoshida
patent: 5604159 (1997-02-01), Cooper et al.
patent: 5608248 (1997-03-01), Ohno
patent: 5763931 (1998-06-01), Sugiyama
patent: 5830797 (1998-11-01), Cleeves
patent: 5831305 (1998-11-01), Kim
patent: 5846854 (1998-12-01), Giraud et al.
patent: 6004865 (1999-12-01), Horiuchi et al.
patent: 6091129 (2000-07-01), Cleeves
patent: 6117760 (2000-09-01), Gardner et al.
patent: 6136701 (2000-10-01), Shin
patent: 6274919 (2001-08-01), Wada
patent: 6277708 (2001-08-01), Bothra et al.
patent: 6291286 (2001-09-01), Hsiao
patent: 6373138 (2002-04-01), Noble
patent: 0 720 221 (1996-07-01), None
Kuge et al.,SOI-DRAM Circuit Technologies For Low Power High-Speed Multigiga Scale Memories, IEEE Journal of Solid State Circuits, Apr. 1996, pp. 586-591.
Suma et al.,An SOI-DRAM With Wide Operating Voltage Range by CMOS/SIMOX Technology, IEEE Journal of Solid State Circuits, Nov. 1994, pp. 1323-1329.
Bakeman et al.,A High Performance 16-Mb DRAM Technology, 1990 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, Jun. 4-7, pp. 11-12.
Kohyama et al.,Buried Bit Line Cell for 64MB DRAMs, IEEE 1990 Symposium on VLSI Technology, pp. 17-18.
Davari et al.,A Variable-Size Shallow Trench Isolation(STI)Technology With Diffused Sidewall Doping for Submicron CMOS, IEDM Technical Digest, International Electron Devices Meeting, San Francisco, CA, Dec. 11-14, 1988, pp. 92-95.
Buried Stud that Eliminates Substrate and Well Contact Requirements, IBM Web Page, Jun. 1996, 2 pgs.
Article: SEPIA: A New Isolation Structure for Soft-Error-Immune LSI=s (Feb. 1993).
Gurley Lynne A.
John P.S. Wells St.
Micro)n Technology, Inc.
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