Method for reducing shallow trench isolation edge thinning...

Details Method for reducing shallow trench isolation edge thinning... Method for reducing shallow trench isolation edge thinning...

2002-04-19

2004-11-30

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S275000

Reexamination Certificate

active

06825083

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to a process for reducing shallow trench isolation edge thinning on tunnel oxides for high performance flash memories.
BACKGROUND ART
A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block. A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. Flash memory is used in digital cellular phones, digital cameras, LAN switches, PC Cards for notebook computers, digital set-up boxes, embedded controllers, and other devices.
As flash memory technology progresses, the density of the memory cells, as well as, the speed of the flash memory increases. Device isolation is necessary in order to achieve higher cell densities. Without proper device isolation, local cells as well as peripheral devices will adversely interfere and interact with each other. Device isolation helps reduce parasitic conduction paths, series resistances, current leakage, and helps maintain threshold voltage control.
Shallow trench isolation (STI) is one technique for device isolation. The STI technique improves the scaling of devices in order to increase cell density throughout an integrated circuit. The formation of STI regions precedes the formation of a tunnel oxide layer of the flash memory devices during fabrication of the integrated circuit.
In one integrated circuit comprising flash memory devices and peripheral transistor devices, the peripheral transistors need to handle both high voltages (HV) and low voltages (LV) in order to control the core flash memory devices. The high voltage transistors are peripheral thick gate oxide transistors. The low voltage transistors are peripheral thin gate oxide transistors.
As technology improves, high performance low voltage transistors require thinner and thinner gate oxide layers. In the current process, the formation of the thin gate oxide layer for the low voltage transistors requires several etch and clean steps to remove pre-existent oxide and masking layers, such as the tunnel oxide layers associated with the flash memory devices, and the thick gate oxide layers for peripheral thick gate oxide transistors.
Prior Art
FIG. 1
is a cross-sectional view of an integrated circuit comprising flash memory devices and peripheral thick and thin gate oxide transistors. Prior Art
FIG. 1
illustrates three stages of fabrication for thin gate oxide transistors in the integrated circuit. The three stages of fabrication as illustrated are as follows: gate oxide (GATEOX) stage
100
A for the formation of the tunnel oxide layer
140
, GATEOX stage
100
B for the formation of the thick gate oxide layer
130
, and GATEOX stage
100
C for the formation of the thin gate oxide layer
120
.
The portions illustrated in the thin gate oxide transistor devices include an STI region
190
for separating devices within the integrated circuit. The STI region
190
of Prior Art
FIG. 1
isolates two thin gate oxide transistor devices, located on either side of the STI region
190
. Active regions
180
of the thin gate oxide transistor devices are shown and contain either the source or drain for the devices.
At the GATEOX stage
100
A, a tunnel oxide layer
140
is formed on top of the active region
180
of the thin gate oxide transistor devices. Prior to tunnel oxide layer
140
formation, an overetch and clean process was performed to expose the silicon surface in the active areas
180
of the thin gate oxide transistors. The silicon surface of the transistor devices lies along line
150
in Prior Art FIG.
1
.
As a result, a recess of the silicon surface along line
150
for each of the thin gate oxide transistor devices, as well as recess of the field oxide in the STI region
190
, occurs. The recess of silicon, hereinafter referred to as “STI recess,” is especially pronounced at the edges of the STI region (e.g., STI corner
105
A, as indicated in shadow). The STI recess is more pronounced at STI corner
105
A due to the increased slope of the silicon surface at the STI corner
105
A, in comparison to the slope of the silicon surface that lies parallel and along line
150
.
Furthermore, because of the overetch and clean process, STI recess leads to subsequent edge thinning of any oxide deposition, such as the tunnel oxide layer
140
, at the STI corners. Reduced formation of subsequent oxide layers is also due to the increased slope of the silicon surface at the STI corner
105
A. This is evidenced by the reduced deposition thickness
115
A of tunnel oxide layer
140
at the STI corner
105
A, as opposed to the thickness
110
A of the tunnel oxide layer
140
at the surface of the silicon that is parallel with line
150
.
Because the thin oxide transistor devices on either side of the STI region
190
are thin gate oxide devices, the tunnel oxide layer is removed in subsequent fabrication steps to facilitate the formation of a thin gate oxide layer
120
.
However, subsequent overetching and cleaning steps due to the formation and removal of intermediate oxide layers lead to further STI recess in the STI corners
105
A,
105
B, and
105
C. For example, at the GATEOX stage
100
B, a thick gate oxide layer
130
is formed on top of the active region
180
of the thin gate oxide transistor devices. Prior to the thick gate oxide layer
130
formation, an overetch and clean process was performed to again expose the silicon surface in the active areas
180
of the thin gate oxide transistor in order to facilitate bonding between the silicon surface and the newly formed oxide layer. The silicon surface of the transistor devices lies along line
150
in Prior Art FIG.
1
.
The GATEOX stage
100
B of Prior Art
FIG. 1
illustrates the further recess of silicon due to the overetching and cleaning performed prior to the formation of the thick gate oxide layer
130
in the STI corner
105
B. The STI recess is more pronounced at GATEOX stage
100
B, in comparison to GATEOX stage
100
A, as the silicon surface in the STI corner
105
B has a longer and more rounded surface leading to further edge thinning of later formed oxide layers. For example, the STI recess in the STI corner
1051
B reaches down to the line
155
at GATEOX stage
100
B, as opposed to the STI recess at GATEOX stage
100
A, where the STI recess occurs more at the surface near line
150
.
In order to form the thin gate oxide layer
120
on the thin gate oxide transistors located on either side of the STI region
190
, a further overetching and cleaning leads again to further STI recess, as evidenced in the STI corner
105
C of GATEOX stage
100
C. The STI recess is most pronounced at GATEOX stage
100
C, as the silicon surface in the STI corner
105
C has the longest and most rounded surface. This leads to further edge thinning of subsequently formed thin gate oxide layer
120
.
For example, the STI recess in the STI corner
105
C at GATEOX stage
100
C reaches down past the line
155
, as opposed to the STI recess at GATEOX stage
100
B, where the STI recess reaches only to line
155
. The formation of the thin gate oxide layer at the STI corners is most adversely affected, as evidenced by the extreme thinning of the thin gate oxide layer
120
at the STI corner
105
C. This is evidenced by the reduced deposition thickness
115
C of thin gate oxide layer
120
at the STI corner
105
C, as opposed to the thickness
110
C of the thin gate oxide layer
140
at the surface of the silicon that is parallel with line
150
.
The reduced edge thinning of th

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