Silicide process using high K-dielectrics

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S412000

Reexamination Certificate

active

06784506

ABSTRACT:

FIELD OF INVENTION
This application pertains to a transistor with a gate electrode having a high-K gate dielectric with a nickel silicide layer and method of making the same.
BACKGROUND OF THE INVENTION
Standard gate semiconductor structures such as transistors and memory units are well known in the semiconductor device industry. Typically, to form a standard gate electrode, first a gate dielectric layer comprising silicon dioxide is formed on an active surface of a semiconductor substrate between isolation regions and then a polysilicon layer is formed on the dielectric layer. The layers of materials are then etched in a controlled manner to define the borders of the gate electrode. Source and drain regions are formed by doping the active surface of the substrate by ion doping by well know techniques. Dielectric sidewall spacers are formed on the side surfaces of the gate electrode to complete the device.
As both the vertical and lateral device dimensions decrease into the deep sub-micron range such as that associated with the formation of ultra-large scale integration (ULSI) devices, problems arise such as junction leakage and increased sheet resistance of the contact areas to the source and drain regions. To overcome these problems, the use of self-aligned, highly electrically conductive refractory metal silicides, i.e., “salicides” (derived from Self-ALIgned-siliCIDE), has become commonplace in the manufacture of IC semiconductor devices comprising, e.g., MOS type transistors. Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon (Si). The metal does not react with silicon oxides, nitrides, or oxynitrides under normal processing conditions. Refractory metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each of which forms very low resistively phases with Si, e.g., PtSi
2
, TiSi
2
, NiSi, and CoSi
2
. In practice, the refractory metal is deposited in a uniform thickness over all exposed surface features of a Si wafer, preferably by means of physical vapor deposition (“PVD”) process, e.g., sputtering from an ultra-pure target utilizing an ultra-high vacuum, multi-chamber DC magnetron sputtering system. Upon thermal processing, e.g., a rapid thermal annealing (“RTA”) performed in an inert atmosphere, the refractory metal layer reacts with underlying Si to form an electrically conductive refractory metal silicide layer on the top surface of the polysilicon gate electrode as well as on the exposed surfaces of the substrate where source and drain regions are formed. Unreacted portions of the refractory metal layer, e.g., on the dielectric sidewall spacers and the silicon oxide isolation regions, are removed, as by a wet chemical etching process.
Also associated with the fabrication of ULSI devices, the thickness of the silicon dioxide dielectric for the gate electrode is rapidly approaching a thickness of 40 Å or less. At this thickness, the use of silicon dioxide as a gate dielectric is limited because direct tunneling may occur through the gate dielectric to the channel region, wherein current leaks from the gate electrode and the channel region. Such leakage of current causes an increase in power consumption. Because of this problem, alternative methods have been sought to reduce leakage current.
One such method is to use high-K dielectrics for gate dielectric materials. A high-K dielectric is any dielectric material having a dielectric constant greater than silicon dioxide that is 3.8. The dielectric constant of the high-K dielectric is preferably greater than 5.0, and more preferably, greater than 20.0. However, the use of high-K dielectrics for gate dielectric materials is disadvantageous because the high processing temperatures required for forming the salicide layer causes the dielectric to decompose due to the reaction of the dielectric with silicon in the semiconductor substrate and the polysilicon in the gate.
It has been discovered that by forming nickel silicide, the aforementioned problems are overcome. Lower temperatures are required to form nickel silicide, than for the other refractory metals. Also, Ni as opposed to other refractory metals such as Ti diffuses into Si, which helps to limit bridging between the metal silicide layer on the gate electrode and a metal silicide layer on the associated source/drain regions. Further, the formation of nickel silicide requires less Si than other refractory metals, such as Ti or Co. Nickel silicide also exhibits almost no line width dependence on sheet resistance. Advantageously, nickel silicide is normally annealed in a one step process, rather than the more complex process required in TiSi
2
and CoSi
2
salicide technology. Finally, nickel silicide exhibits lower film stress, i.e., causes less wafer distortion than conventional Ti or Co silicides.
SUMMARY OF THE INVENTION
An object of this invention is to provide for the formation of a self-aligned metal silicide on the gate, source and drain electrodes without deterioration of the high-K dielectric of the gate electrode. Another object is to provide for a nickel-silicide on a gate electrode including a high-K dielectric. A further object is to provide for a nickel silicide layer on the gate electrode being included a high-K dielectric material. Other objects, features and advantages of this invention will become apparent upon reading the following detailed description and referring to the accompanying drawing.


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