Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-10-30

2004-02-24

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S201000, C365S220000

Reexamination Certificate

active

06697285

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-071106, filed Mar. 13, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly, to a data output circuit section of a semiconductor memory, which is used in, for example, a ROM (Read Only Memory).
2. Description of the Related Art
In recent years, the memory capacity of the semiconductor memory is made greater and greater. In this connection, the test time of the semiconductor memory is made very long, with the result that it is very important to shorten the test time. For shortening the test time, required is an improvement in the rate of data read denoting how much data can be read in a predetermined time. In the conventional semiconductor memory, however, no particular measure was taken for improving the rate of data read in the semiconductor memory device itself.
Disclosed in Japanese Patent Disclosure (Kokai) No. 2000-11695 is a semiconductor memory device provided with a built-in parallel test circuit. It is taught that an internal clock signal is prepared from an external clock signal in a wafer test operation mode so as to output two groups of data in synchronism with the internal clock signal. However, the compatibility with a general purpose memory and the application to the test under the packaged state are not referred to at all in this prior art.
As described above, the conventional semiconductor memory device gives rise to the problem that no measure is taken for improving the rate of data read for shortening the test time.
An object of the present invention, which is intended to overcome the above-noted problem inherent in the prior art, is to provide a semiconductor memory device capable of improving the rate of data read or the rate of data write so as to shorten the time required for the test while maintaining the compatibility with the general purpose memory and without increasing the number of external terminals.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell array; a plurality of data output terminals for outputting in parallel data of a plurality of bits; a latch circuit arranged between the memory cell array and the plural data output terminals; a read control circuit for reading in parallel from the memory cell array data of bits, the number of the bits being a plurality of times as large as the number of the plural data output terminals; an address transition detecting circuit for detecting the transition of an address signal for outputting a latch control signal; and an output control circuit for performing a switching control on the basis of a switching signal such that the data read in parallel from the memory cell array in each read cycle is held by the latch circuit in accordance with the latch control signal, and the data held by the latch circuit is divided by a plural number and one group of the divided data is outputted to the plural data output terminals during the cycle, with the remaining group of divided data being outputted to the plural data output terminals during a predetermined period of the next read cycle.
According to a second aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell array; a plurality of data output terminals for outputting in parallel data of a plurality of bits; a latch circuit arranged between the memory cell array and the plural data output terminals; a read control circuit for reading in parallel from the memory cell array data of bits, the number of the bits being a plurality of times as large as the number of the plural data output terminals; an address transition detecting circuit for detecting the transition of an address signal for outputting a latch control signal; and an output control circuit for performing a switching control on the basis of a switching signal such that the data read in parallel from the memory cell array in each read cycle during the normal operation and during the test operation is held by the latch circuit in accordance with the latch control signal, and the data held by the latch circuit is divided by a plural number and the divided groups of data are outputted group by group to the plural data output terminals during a predetermined period of the next read cycle.
Further, according to a third aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell array; a plurality of data output terminals for outputting in parallel data of a plurality of bits; a latch circuit arranged between the memory cell array and the plural data output terminals; a read control circuit for reading in parallel from the plural memory cell array data of bits, the number of the bits being a plurality of times as large as the number of the plural data output terminals; an address transition detecting circuit for detecting the transition of an address signal for outputting a latch control signal; and an output control circuit for performing a switching control on the basis of a switching signal such that the data read in parallel from the memory cell array in each read cycle is held by the latch circuit in accordance with the latch control signal, and the data held by the latch circuit is divided by a plural number, one group of the divided data being outputted to the plural data output terminals during the cycle and the remaining group of data being outputted to the plural data output terminals during a predetermined period of the next cycle during normal operation, and the divided groups of data being outputted group by group to the plural data output terminals during a predetermined period of the next read cycle during the test operation.


REFERENCES:
patent: 5751645 (1998-05-01), Tsukikawa
patent: 6577534 (2003-06-01), Tsuruda
patent: 6577551 (2003-06-01), Ito et al.
patent: P2000-11695 (2000-01-01), None

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