Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-17
2004-11-16
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S366000
Reexamination Certificate
active
06818492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a transistor device with improved high-frequency characteristics and a manufacturing method thereof.
2. Description of the Related Art
A structure of a general NPN-type planar transistor is shown in FIG.
17
. Namely, on the surface of an N-type collector layer
51
comprising an N
+
-type semiconductor layer, a P-type base region
53
is formed, an N
+
-type emitter region
54
is formed on the surface of the base region
53
, and the surface is coated with a silicon oxide film
55
. Opening portions are formed on the silicon oxide film
55
so as to become contact holes and a base electrode
56
and an emitter electrode
57
are formed. Since high-frequency characteristics mainly depend on the base width W
b
, a graft base-type structure where a P
+
-type external base region
58
is provided on the periphery of the emitter region
54
is employed. With this shape, a narrow base width W
b
is obtainable and, at the same time, curvature of a depletion layer extending over base-collector junctions is decreased, and base resistance r
b
can be reduced.
In addition, in order to obtain a shallow base width W
b
, a shallow emitter junction is indispensable, therefore, formation of the emitter region
54
by impurity diffusion from a polysilicon layer with impurities doped has been carried out (for example, Japanese Laid-Open Patent Application No. Hei 7-142497).
However, the graft base type has problems such that, since the base region
53
and the external base region
58
are formed by different processes, the processes become complicated and since the shallow base region
53
is formed by thermal diffusion, the diffusion depth thereof easily becomes uneven and unevenness in the high-frequency characteristics also increases.
In order to solve such problems, as shown in
FIG. 18
, a method has been also carried out wherein a sidewall
68
is provided on the inside wall of a trench
62
formed on the base region
63
, a diffusion source layer
60
for forming an emitter region is formed on the trench
62
, and impurities are diffused from the base region
63
which is exposed at the bottom portion of the trench
62
so that an emitter region
64
is formed (for example, Japanese Laid-Open Patent Application No. 2000-252290).
In a transistor shown in
FIG. 18
, since the emitter region
64
is formed on the bottom portion of the trench
62
, therefore, the base width W
b
can be controlled by the length of trench
62
. In order to obtain an extremely shallow junction by thermal diffusion, it is necessary to lower the impurity concentration, therefore unevenness occurs, whereas the impurity concentration of the base region
63
can be higher owing to the trench
62
to some extent, whereby unevenness in the base width W
b
can be reduced. In addition, since formation of an external base region is unnecessary, the processes also become simple.
However, a base electrode
69
is grounded only via a contact hole, the distance between the base electrode
69
and an active region of the base immediately under the emitter region
64
where carriers move is long and the grounded area is also small, therefore there has been a limit to any further reduction in base resistance r
b
.
Furthermore, the capacitance C
BE
is related to the area of the emitter region
64
, and r
b
and C
BE
greatly affect f
T
, which is a cut-off frequency, therefore, reductions in these have been demanded.
SUMMARY OF THE INVENTION
This invention provides a semiconductor device comprising a first conducting type base region formed on the surface of a second conducting type collector layer, a trench provided on the surface of the base region, a second conducting type emitter region formed on the surface of the base region which is exposed at the bottom portion of the trench, a sidewall provided on the inside wall of the trench, and an electrode in contact with the whole surface of the base region excluding the trench. In this configuration, a base electrode layer is provided from the side surface of the trench to the whole surface of the base region, therefore the distance between the active region of the base immediately under the emitter region and the base electrode can be reduced and also the grounded area of the base electrode increases. Namely, the base resistance r
b
can be drastically reduced.
Moreover, due to the sidewall provided for the trench, the bottom portion of the trench becomes narrower than the opening portion thereof, therefore the area of the emitter region formed on the bottom portion is reduced, thus realizing a reduction in the capacitance content C
BE
.
Also, a method for manufacturing a semiconductor device of this invention comprises steps of forming a first conducting type base region on the surface of a second conducting type collector layer, forming a base electrode layer on the surface of the base region and forming an insulating film on the surface of this base electrode layer, forming a trench, which does not reach the collector layer, on the base region by creating an opening at a part of the base electrode layer and the insulating film and forming a sidewall on the inside wall of the trench, forming a polysilicon layer containing impurities for emitter diffusion inside the trench, forming an emitter region by diffusing the impurities from the polysilicon layer, and forming a through hole on the insulating film so as to form a base electrode which comes into contact with the base electrode layer and, at the same time, forming an emitter electrode which comes into contact with the polysilicon layer. According to this method, by providing the sidewall for the trench and performing emitter diffusion, the emitter region which is finer than the limit of a photo-etching technique can be formed, thus a transistor device which is superior in the high-frequency characteristics can be manufactured.
Moreover, a method for manufacturing a semiconductor device of this invention comprises steps of preparing a first conducting type collector layer, forming a base electrode layer made of polysilicon containing second conducting type impurities on the surface of the collector layer and forming an insulating film on the surface of this base electrode layer, forming a trench on the collector layer by creating an opening at a part of the base electrode layer and the insulating film and doping second conducting type impurities into the whole surface, forming a sidewall on the inside wall of the trench, forming a polysilicon layer containing impurities for emitter diffusion inside the trench, diffusing the impurities in the periphery of the trench and underneath the base electrode layer for forming a base region and, at the same time, diffusing the impurities from the polysilicon layer for forming an emitter region, forming a through hole on the insulating film and forming a base electrode which comes into contact with the base electrode layer and, at the same time, forming an emitter electrode which comes into contact with the polysilicon layer. According to this methods, the active region of the base immediately under the emitter is formed by diffusing the impurities doped in the periphery of the trench, thus a transistor device which has less unevenness in spite of a shallow junction can be manufactured.
This invention provides a semiconductor structure by which, first, the base resistance r
b
can be substantially reduced. The trench is formed using the base electrode layer and the oxide film which are provided on the whole surface as a mask, whereby the trench and the base electrode layer become adjacent to each other. Since carriers move between the active region of the base immediately under the emitter and the base electrode layer, in comparison to the prior art where grounding is carried out only at a contact hole, not only can the distance be substantially shortened but also the grounded area is greatly increased. Th
Kubo Hirotoshi
Murai Shigeyuki
Sawame Hidetaka
Tominaga Hisaaki
Ghyka Alexander
Morrison & Foerster / LLP
Sanyo Electric Co,. Ltd.
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