Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-02
2004-06-01
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000, C438S396000
Reexamination Certificate
active
06743672
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing semiconductor memory device; and, more particularly, to a method for manufacturing a capacitor.
DESCRIPTION OF THE BACKGROUND ART
Recently, researches for adapting a BST [(Ba,Sr)TiO
3
] layer, which has a high dielectric constant as an insulating material for a capacitor for a dynamic random access memory (DRAM) of Giga level, have been proceeded.
Especially, a three-dimensional storage node or a concave structure capacitor has been used in a device having a cell size of below 0.10 &mgr;m using the BST layer as an insulating material. At this time, materials such as Pt, Ru and Ir, etc., are used as electrodes. When carrying out an etching process using those materials as storage nodes, an etching profile is not better than an SiO
2
layer, so it is difficult to adapt those materials to a cell size of below 0.10 &mgr;m.
To solve the above-mentioned problems, a capacitor may be manufactured in a concave structure or manufactured by forming a bottom electrode using an electro plating (EP) method. The capacitors are used to store a data within DRAM that is a main memory of a computer, and especially, the capacitor of the present invention may be used in a DRAM that is over a Giga level.
FIGS. 1A
to
1
D are cross-sectional views illustrating a conventional method for manufacturing a capacitor.
Referring to
FIG. 1A
, a transistor manufacturing process is carried out on a semiconductor substrate
11
. First, a word line (not shown) and a source/drain region
12
are formed on the semiconductor substrate
11
. Then, a first SiO
2
layer
13
and an Si
3
N
4
layer
14
that are interlayer insulating layers are successively formed on the semiconductor substrate
11
. In here, the Si
3
N
4
layer
14
is an etching barrier layer for preventing an etching of the first SiO
2
layer
13
when a dry etching process is applied to a seed layer
19
and an adhesion layer
18
.
Next, a contact hole, which exposes a predetermined portion of the source/drain region
12
, is formed by selectively etching the Si
3
N
4
layer
14
and the first SiO
2
layer
13
. Subsequently, polysilicon is deposited on the resulting structure including in the contact hole. Then, a polysilicon plug
15
is formed in the contact hole using an etchback process so that the polysilicon plug
15
partly fills the contact hole.
A TiSi
2
layer
16
is formed on the polysilicon plug
15
and a first TiN layer
17
is formed on the TiSi
2
layer
16
, and then the first TiN layer
17
and TiSi2
16
are completely filled into the contact hole using a CMP process. At this time, the TiSi
2
layer
16
is formed in an interface between the polysilicon plug
15
and the TiN layer
17
after a predetermined thermal process through depositing the TiN layer
17
.
A second TiN layer
18
and a Pt seed layer
19
, which function as “adhesive layers,” are successively formed on the Si
3
N
4
layer
14
including the first TiN layer
17
. A second SiO
2
layer
20
is formed on the Pt seed layer
19
as a capacitor oxide layer.
In here, the second TiN layer
18
is used to increase adhesiveness between the Si
3
N
4
layer
14
and a bottom electrode. The Pt seed layer
19
is a seed layer to form a bottom electrode with the EP method and is formed using the physical vapor deposition (PVD) method.
A second SiO
2
layer
20
is formed over the Pt seed layer
19
and selectively etched to expose a predetermined portion of the Pt seed layer
19
where a storage node region is formed.
Referring to
FIG. 1B
, a bias is applied to the Pt seed layer
19
and a Pt bottom electrode
21
is formed on the exposed Pt seed layer
19
using the EP method. Subsequently, the Pt electrode
21
is separated until a surface of the second SiO
2
layer
20
is exposed using an etchback or a CMP method, and then the second SiO
2
layer
20
is removed.
Referring to
FIG. 1C
, the Pt electrode
21
is completely separated from other Pt electrodes
21
by selectively etching the Pt seed layer
19
and the second TiN layer
18
. At this time, a stacked layer of a Pt seed layer
19
A and a second TiN layer
18
A remain on the bottom portion of the Pt electrode
21
. Further, the Pt electrode
21
has an overhang formation that has relatively larger width on its top portion than that on the bottom portion.
Referring to
FIG. 1D
, a BST layer
22
is deposited on a resulting structure including the Pt electrode
21
using the chemical vapor deposition (CVD) method and a top electrode
23
is deposited using the CVD method.
In the above-mentioned conventional method, the second SiO
2
layer
20
, which is a capacitor oxide layer, is etched to form the Pt electrode
21
using an EP and the Pt electrode
21
is formed in the etched portion. At this time, an etching portion of the SiO
2
layer
20
may not have a vertical etching profile of 90°, and the SiO
2
layer
20
has an overhang formation so that a top portion of a bottom electrode is thicker than a bottom portion (Refer to FIG.
1
C).
In case where the above-mentioned structure is adapted in a DRAM device, which is over a Giga level, if a serious overhang results even though a layer is formed by the CVD method, a bad topology is caused, and it may be impossible to have an enough space to deposit a dielectric layer or a top electrode.
Also, a seed layer is needed to form the Pt electrode
21
using the EP method. In other words, in a conventional method, the Pt electrode
21
is formed on a seed layer after the seed layer is deposited using the EP method and an etchback process is carried out to separate the Pt electrodes from each other. Further, the seed layer is separated.
However, if the seed layer is not completely removed during the etchback process, but remains within a residue formation, the Pt electrode
21
is re-deposited on the residue of the seed layer.
This results in the pt layer having bad film characteristics, which cause a problem in forming charges on both sides of the dielectric layer and have effect on characteristics and operations of a capacitor.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a capacitor capable of preventing residue in a seed layer and solving difficulty in obtaining a space for depositing a post insulating layer and a top electrode, being caused by an overhang in forming a bottom electrode which is formed through the electro plating (EP) method.
In accordance with one embodiment of the present invention, there is provided a method for manufacturing a capacitor including the steps of: A method for manufacturing a capacitor, comprising the steps of: forming a seed layer on a semiconductor substrate; forming a first insulating layer on the seed layer, the first insulating layer having a first etch property; forming a first opening unit by selectively etching the first insulating layer and the seed layer; forming a second insulating layer having a second etch property in the first opening unit; removing the first insulating layer using an etching which uses a selective etching ratio between the first insulating layer and the second insulating layer so that the seed layer is exposed; forming a bottom electrode on the exposed seed layer using an electro plating (EP) method; and removing the second insulating layer.
In accordance with a second embodiment of the present invention, there is provided a method for manufacturing a capacitor including the steps of: forming a first insulating layer on a semiconductor substrate; forming a contact hole by selectively etching the first insulating layer; filling the contact hole with a plug and a barrier layer over the plug; on the first insulating layer and the barrier layer, forming an adhesive layer, a seed layer and a second insulating layer having a first etch property, successively; forming an opening unit which has relatively small width in a bottom portion than a top portion by selectively etching the second insulating layer and the seed layer; forming a third ins
LandOfFree
Method for manufacturing a capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3349936