Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2003-07-28
2004-11-02
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S205000, C365S149000
Reexamination Certificate
active
06813205
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to a pre-charge and sense-out circuit, and more particularly, to a pre-charge and sense-out circuit used for a differential type ROM with a charge-sharing module.
2. Description of the Prior Art
Among various applications of electronic products, memory chips are always an important and essential component. According to how data is treated after the removal of power, memory chips used today is divided into two types volatile or non-volatile. Volatile memory is a data storage device that offers the advantage of high-access speed which can be used as a buffer between a high-speed cell processor and other parts of the circuit but at the cost of losing digital data when power is removed. Examples of volatile memory include DRAM and SDRAM. Non-volatile memory is a data storage device that offers the advantage of retaining digital data even when power is removed but at the cost of having an access speed that is slower than that of volatile memory. Examples of non-volatile memory include ROMs and flash memory.
The application field for memory chips is vast. As technology advances, so too does the application field for memory chips. Besides functioning as data storage devices for personal computers, memory chips are also used in a variety of electronic products such as laptop computers, personal digital assistants (PDAs), cell phones, and digital cameras.
Typical memory chips installed in an electronic product have three major modes of operation writing (programming), erasing, and reading. Which mode of operation the memory is in is dependent on the control signal from the electronic product. Memory chips will switch to the writing mode when the electronic product writes digital data into a specific storing address in the memory as indicated by the control signal. Memory chips will switch to the erasing mode when the electronic product erases digital data from a specific storing address in the memory as indicated by the control signal. Finally, memory chips will switch to the reading mode when the electronic product reads digital data from a specific storing address in the memory as indicated by the control signal.
A memory chip is usually comprised of a sense-out circuit (or a sensing amplifier) electrically connected to a memory-cell array used for the storing of digital data or the sending out of stored data from a specific storing address within the memory-cell array as indicated by the control signal. The architecture of a sense-out circuit was published in IEEE International SOI Conference, p.143-144, Oct. 1, 2001.
FIG. 1
shows a sense-out circuit of a differential type ROM according to prior art. The differential type ROM is comprised of a sense-out circuit
10
and a memory-cell array
20
, wherein the memory-cell array
20
includes a plurality of memory cells
22
. The addresses within a memory cell
22
is defined by a plurality of word lines WL
1
~WLn and a plurality of pairs of bit lines (BL
11
, BL
12
)~(BL
m1
, BL
m2
). In other words the intersections between each word line and pair of bit lines are electrically connected to a memory cell
22
.
FIG. 1
shows a memory-cell array
22
that can be composed of any number of memory cells
22
stacked one on top of another as indicated by the dotted line between the first and last memory cells
22
. For simplicity though, the following descriptions will treat the memory cell array
20
as having two memory cells
22
. Each memory cell is physically composed of two NMOS transistors. The gate of each transistor within the same memory cell is electrically connected to the same word line; however, the drain of each transistor within the same memory cell is electrically connected to different bit line in a pair of bit lines. For example in
FIG. 1
, the drains of the left transistors are electrically connected to the left bit line BL
11
, and the drains of the right transistors are electrically connected to the right bit line BL
12
.
Before writing data to a memory cell
22
, the sources of both NMOS transistors must be grounded. To write logical data into a memory cell
22
, the connection between one of the NMOS transistors and bit lines must be cut by some means such as with a laser. Whatever connection is destroyed gives the memory cell its logical value. Severing the connection between the left transistor and the left bit line assigns a logical value of “1” to the memory cell. Severing the connection between the right transistor and right bit line assigns a logical value of “0” to the memory cell. For example, the top memory cell
22
of
FIG. 1
(X represents a severed connection), has a logical value of “1” while the bottom memory cell
22
has a logical value of “0”.
The pair of bit lines BL
11
, BL
12
is electrically connected to a pre-charge module
12
within the sense-out circuit
10
. (Remember the pair of bit lines (BL
11
, BL
12
) is only the first pair of a plurality of bit lines ranging from (BL
11
, BL
12
)~(BL
m1
, BL
m2
) all of which are connected and function in the same way). The pre-charge module
12
is used to pre-charge the pair of bit lines BL
11
, BL
12
. A pair of data lines, DL
1
, DL
2
is electrically connected to a different pre-charge module
16
within the same sense-out circuit. This second pre-charge module is used to pre-charge the two data lines, DL
1
, DL
2
. A selecting module
14
is located between the two pre-charge modules and serves to electrically connect the pair of bit lines to the two data lines i.e. BL
11
to DL
1
and BL
12
to DL
2
. The purposes of the selecting module is to transmit signals between the bit lines and the data lines according to the first control signal Y
1
and to produce an output signal corresponding to the logical data stored in the memory cell
22
to the two data lines DL, DL
2
.
When the memory chip reads the data, only one memory cell is selected at a time. This means that only one pair from the plurality of pairs of bit lines (BL
11
, BL
12
)~(BL
m1
, BL
m2
) is selected, and only one word line from the plurality of word lines within the selected pair of bit lines is chosen. For example in
FIG. 1
, the selection of the pair of the bit lines BL
11
, BL
12
and the word line WL
1
gives the data in the top memory cell
22
to the chip to read. To ensure the data from the top memory cell in
FIG. 1
along the pair of bit lines BL
11
, BL
12
is properly read without error, the selecting module
14
in the prior sense-out circuit
10
uses a high-V
TH
device to separate the pairs of bit lines and data lines. By doing so, effects of current leakage from memory cells
22
on unselected pairs of bit lines connected to the same sense-out circuit
10
in this case (BL
21
, BL
22
)~(BL
m1
, BL
m2
) is prevented.
But there is a disadvantage for using the high-V
TH
device in the selecting module
14
. Generally, the turn-on time of the high-V
TH
device is longer than the rest of the parts in the memory chip. As a result when the control signal Y
1
instructs the memory chip to read data and turn on the high-V
TH
device, the operational time becomes longer. Thus, the access time of the memory chip will be substantially affected.
SUMMARY OF INVENTION
It is therefore the primary objective of the claimed invention to provide a pre-charge and sense-out circuit, which contains a charge-sharing module, to solve the above-mentioned problem.
According to the claimed invention, a pre-charge and sense-out circuit of a differential type ROM is disclosed for sensing logical data stored in a memory cell of the ROM, the memory cell being capable of connecting and then sending digital signals along either one of a pair of bit lines. The pre-charge and sense-out circuit is comprised of:
1) A pre-charge module electrically connected to a pair of bit lines connected to the memory cell for the purpose of pre-charging the said pair of bit lines
2) A selecting module electrically connected to the above-mentioned pair of bit lines and two data lines where each bit line corresponds to a unique and separate d
Auduong Gene N.
Hsu Winston
Mediatek Incorporation
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