Method of forming an STI feature while avoiding or reducing...

Details Method of forming an STI feature while avoiding or reducing... Method of forming an STI feature while avoiding or reducing...

2002-10-11

2004-02-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S433000, C438S435000, C438S738000, C438S744000, C438S950000, C257S506000, C257S509000, C257S510000, C257S513000, C257S635000, C257S640000, C257S647000

Reexamination Certificate

active

06689665

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to semiconductor processing methods and more particularly to a method for forming shallow trench isolation structures while avoiding or reducing divot formation at STI trench corners.
BACKGROUND OF THE INVENTION
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is a preferred electrical isolation technique especially for a semiconductor chip with high integration. STI structures can be made using a variety of methods including, for example, the Buried Oxide (BOX) isolation method for shallow trenches. The BOX method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO
2
) which is then planarized by a plasma etched back process and/or a chemical mechanical polishing (CMP) process to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the substrate, for example, silicon, and are typically between about 0.3 and about 1.0 microns deep.
Shallow trench isolation features with trenches having submicrometer dimensions are effective in preventing latch-up and punch-through phenomena. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask, for example silicon nitride, over the targeted trench layer, for example including a thermally grown pad oxide layer, patterning a photoresist over the hard mask to define a trench feature, anisotropically etching the hard mask to form a patterned hard mask, and thereafter anisotropically etching the trench feature to form the shallow trench isolation feature. Subsequently, the photoresist is removed (e.g., stripped) and the shallow trench isolation feature is back-filled, with a dielectric material, for example a CVD silicon dioxide, also referred to as STI oxide, followed by thermal treatment and planarization steps to remove excess materials remaining above the trench level.
In the STI technique, the shallow trench isolation area is first defined to form STI trenches anisotropically etched into the silicon substrate through overlying layers including a pad oxide layer and a hardmask metal nitride layer, for example silicon nitride, overlying the pad oxide layer. The STI trench is then lined with for example, a thermally grown silicon dioxide layer, also referred to as an oxide trench liner, grown over the exposed silicon substrate forming the trench surfaces. The STI trench is then back filled with a chemical vapor deposited (CVD) oxide and chemically mechanically polished (CMP) back to the hardmask layer also functioning as a CMP polish stop layer to form a planar surface. The hardmask layer is then removed according to a first acidic wet etching procedure followed by a second acidic wet etching procedure to remove the pad oxide layer.
One problem with the prior art STI feature formation process is that during the acidic wet etching processes to remove the hardmask layer and the pad oxide layer, unintentional over etching of the hardmask layer and/or the pad oxide layer frequently occurs leading to divot formation, for example, at the STI trench corners, where the oxide material, for example, the trench oxide liner, is susceptible to etching by, for example, hydrofluoric (HF) acid used to remove the pad oxide layer. The formation of such etching defects adversely affects the electrical integrity of semiconductor devices in a number of ways such as, example, altering the threshold voltage of a field effect transistor (FET), altering the device off-state current, and making the device susceptible to reverse short channel effects.
For example, referring to
FIGS. 1A-1E
are shown cross-sectional side views of formation of typical trench isolation structures at stages in an STI manufacturing process. Referring to
FIG. 1A
are shown STI trenches
12
A and
12
B formed by an anisotropic etching process etching through silicon nitride layer
14
B and thermally grown pad oxide layer
14
A grown over silicon substrate
12
and about 3000 to about 5000 Angstroms into the silicon substrate
12
. Referring to
FIG. 1B
, STI trenches
12
A and
12
B have a thermally grown oxide liner
16
formed over the sidewall and bottom portions of the STI trench over the exposed silicon substrate by a high temperature annealing process in an oxygen containing ambient carried out at about 800° C. to about 1150° C.
Referring to
FIG. 1C
, the STI trenches
12
A and
12
B are subsequently back-filled with a silicon dioxide fill material, for example, by a high density plasma (HDP-CVD) process to form STI oxide layer
18
(oxide liner
16
not shown). Referring to
FIG. 1D
, a CMP process is carried out to polish back the excess STI oxide layer
18
overlying the silicon nitride layer
14
B, the silicon nitride layer
14
B, also acting as a polishing stop. Referring to
FIG. 1E
, a hot phosphoric acid (H
3
PO
4
) wet etchant solution, for example at about 150° C. is used to remove silicon nitride layer
14
B and a hydrofluoric acid (HF) wet etchant solution is then used to remove the pad oxide layer
14
A. During the pad oxide wet etching process, over etching, particularly at the STI trench corners can occur forming divots (e.g.,
12
C,
12
D) at the STI trench corners extending into the STI back filled trenches due to preferential over etching of the oxide trench liner
16
during the hydrofluoric acid (HF) wet etching process to remove the pad oxide. The trench corners are particularly susceptible to divot formation by preferential etching during the HF etching process. As a result, electrical performance shortcomings in a semiconductor device are experienced including what is known in the art as off-state current and reverse short channel effects caused by high electric fields at the trench corners.
There is therefore a need in the semiconductor processing art to develop a method of forming shallow trench isolation features that will reduce or avoid the problem of divot formation at the STI trench corners thereby overcoming electrical performance shortcomings is a completed semiconductor device.
It is therefore an object of the invention to provide a method of forming shallow trench isolation features that will reduce or avoid the problem of divot formation at the STI trench corners thereby overcoming electrical performance shortcomings is a completed semiconductor device while overcoming other shortcomings of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners.
In a first embodiment, the method includes providing a shallow trench isolation (STI) feature included in a semiconductor process surface the STI feature including an anisotropically etched trench formed into a semiconductor substrate extending through a thickness including a thermally grown silicon dioxide layer overlying the semiconductor substrate and a metal nitride hardmask layer overlying the thermally grown silicon dioxide layer said anisotropically etched trench bei

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