Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-25
2004-02-17
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S304000, C438S231000, C438S336000
Reexamination Certificate
active
06693013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention is directed to a semiconductor transistor using an L-shaped spacer and a method of fabricating the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated, there is an increased demand for a method of suppressing a short channel effect. To this end, a commonly used structure is a lightly doped drain (LDD) structure where a low-concentration junction area is located on a lateral surface of a high-concentration junction area in a drain.
FIG.
1
and
FIG. 2
are sectional diagrams for explaining a method of forming a conventional semiconductor transistor.
Referring now to
FIG. 1
, a gate oxide layer pattern
11
and a gate conductive layer pattern
12
are sequentially formed on a semiconductor substrate
10
. A first oxide layer
13
is formed on the entire surface of the substrate including the gate conductive layer pattern
12
. Using the gate conductive layer pattern
12
as an ion implantation mask, an LDD ion implantation process is carried out to form a low-concentration junction area
16
in the substrate
10
beyond the gate conductive layer pattern
12
.
A silicon nitride layer
14
and a second oxide layer (not shown) are formed on the entire surface of the substrate including the low-concentration junction area
16
. The second oxide layer is anisotropically etched to form a first spacer
15
on a lateral surface of the silicon nitride layer
14
.
Referring now to
FIG. 2
, using the first spacer
15
as an etch mask, the silicon nitride layer
14
is isotropically etched to form an L-shaped second spacer
17
positioned between the first oxide layer
13
and the first spacer
15
. Using the first spacer
15
and the gate conductive layer pattern
12
as an ion implantation mask, a high-concentration ion implantation process is carried out to form a high-concentration junction area
18
in the substrate
10
at both sides of the first spacer
15
. For activation of impurities contained in the high-concentration junction area
18
, an annealing process for the substrate that has undergone a high-concentration ion implantation process is carried out. However, impurities pre-implanted into the low-concentration junction area
16
are also diffused during the annealing process. In order to prevent the diffusion of the pre-implanted impurities, a method changing the order of steps to a high-concentration ion implantation process, an annealing process, and a low-concentration ion implantation process may be employed.
Unfortunately, the resistance of a source/drain region is high due to a low impurity concentration of the low-concentration junction area
16
. A method of forming a medium-concentration junction area between the high- and low-concentration junction areas has been used to overcome this disadvantage.
FIG.
3
through
FIG. 5
are sectional diagrams for explaining a method of forming a medium-concentration junction area between the high- and low-concentration junction areas, according to the prior art. In this case, the low-concentration junction area is formed following an annealing process.
Referring now to
FIG. 3
, a gate oxide layer pattern
51
and a gate conductive layer pattern
52
are sequentially formed on a semiconductor substrate
50
. A nitride layer
55
and a polysilicon layer (not shown) are sequentially formed on the entire surface of the substrate including the gate conductive layer pattern
52
. The polysilicon layer is anisotropically etched to form a first spacer
60
in contact with a sidewall of the nitride layer
55
. An exposed surface of the first spacer
60
, which is made of polysilicon, is oxidized to form a second spacer
62
.
Using the second spacer
62
as an ion implantation mask, a source/drain ion implantation process
80
is carried out to form a high-concentration junction area
81
in the substrate
50
at both sides of the second spacer
62
.
Referring to
FIG. 4
, after forming the high-concentration junction area
81
, the second spacer
62
is removed to expose the first spacer
60
. Using the first spacer
60
as an ion implantation mask, a medium-concentration ion implantation process
82
is carried out to form a medium-concentration junction area
83
in the substrate
50
at both sides of the first spacer
60
. An annealing process is then carried out for the substrate including the medium-concentration junction area
83
.
In
FIG. 5
, after removal of the first spacer
60
, using the sidewall of the nitride layer
55
as an ion implantation mask, a low-concentration ion implantation process
84
is carried out to form a low-concentration junction area
85
in the substrate
50
at both sides of the sidewall of the nitride layer
55
.
Based upon the above-explained method in FIG.
3
through
FIG. 5
, a medium-concentration junction area
83
is formed between low-concentration junction area
85
and high-concentration junction area
81
, thereby reducing the resistance of the source/drain region. Unfortunately, the above-explained method is not efficient in that an ion implantation process must be carried out three times in order to form a medium-concentration junction area between a low- and a high-concentration junction area.
Accordingly, a feature of an embodiment of the present invention is to provide a method of fabricating a semiconductor transistor capable of minimizing the diffusion of impurities in the low-concentration junction area and reducing the resistance of the low-concentration junction area.
Another feature of an embodiment of the present invention is to provide a semiconductor transistor including a low-concentration junction area where impurities are minimally diffused, and including a medium-concentration junction area for reducing the resistance of the low-concentration junction area.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a semiconductor transistor, which undergoes an annealing process and a low-concentration junction area forming process after simultaneously forming medium- and high-concentration junction areas using an L-shaped spacer. In accordance with the present invention, after forming a gate pattern on a semiconductor substrate, a first insulating layer is formed on the resulting structure. L-shaped third and second spacers are sequentially stacked on the first insulating layer that is formed on a sidewall of the gate pattern. Each of the second and third spacers has a horizontal protruding portion.
Using a sidewall of the second spacer and the gate pattern as an ion implantation mask, a high-concentration ion implantation process is carried out to form simultaneously high- and medium-concentration junction areas in the substrate beyond the second spacer and in the substrate under the horizontal protruding portion of the second spacer, respectively. After annealing the semiconductor substrate, which was subjected to the high-concentration ion implantation process, the second spacer is removed. Using a sidewall of the third spacer and the gate pattern as an ion implantation mask, a low-concentration ion implantation process is carried out to form a low-concentration junction area in the substrate under the horizontal protruding portion of the third spacer.
In the formation of the third and second spacers, second, third, and fourth insulating layers are sequentially stacked on the first insulating layer. The fourth insulating layer is anisotropically etched to form a first spacer on the sidewall of the third insulating layer. Using the first spacer as an etch mask, the third insulating layer is etched to form an L-shaped second spacer having a horizontal protruding portion under the first spacer. The second insulating layer is etched during the removal of the first spacer to form an L-shaped third spacer having a horizontal protruding portion under the second spacer.
The medium- and high-concentration junction
Bae Geum-Jong
Choe Tae-Hee
Kim Sang-Su
Ko Young-Gun
Lee Nae-In
Ha Nathan W.
Lee & Sterba, P.C.
Pham Long
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