Flash memory cell with minimized floating gate to...

Details Flash memory cell with minimized floating gate to... Flash memory cell with minimized floating gate to...

2000-11-15

2004-02-17

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S302000, C438S593000, C438S739000

Reexamination Certificate

active

06693009

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to flash memory cells in electrically programmable memory devices, and more particularly, to a flash memory cell with minimized overlap between the floating gate and the drain and/or source bit line junction for minimizing charge leakage from the floating gate to the drain and/or source bit line junction during programming or erasing of the flash memory cell.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a flash memory cell
100
of a prior art flash memory device includes a tunnel dielectric structure
102
typically comprised of silicon dioxide (SiO
2
) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure
102
is disposed on a semiconductor substrate
103
. In addition, a floating gate structure
104
, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure
102
. A floating dielectric structure
106
, typically comprised of silicon dioxide (SiO
2
), is disposed over the floating gate structure
104
. A control gate structure
108
, comprised of a conductive material, is disposed over the floating dielectric structure
106
.
A drain bit line junction
110
that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area
112
of the semiconductor substrate
103
toward a left sidewall of the floating gate structure
104
in
FIG. 1. A
source bit line junction
114
that is doped with the junction dopant is formed within the active device area
112
of the semiconductor substrate
106
toward a right sidewall of the floating gate structure
104
of FIG.
1
. The active device area
112
of the semiconductor substrate
103
is defined by shallow trench isolation structures
116
that electrically isolate the flash memory device
100
from other integrated circuit devices within the semiconductor substrate
103
.
During the program or erase operations of the flash memory cell
100
of
FIG. 1
, charge carriers are injected into or injected out of the floating gate structure
104
. Such variation of the amount of charge carriers within the floating gate structure
104
alters the threshold voltage of the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
For example, when electrons are the charge carriers that are injected into the floating gate structure
104
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the floating gate structure
104
, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell
100
for example, a voltage of+9 Volts is applied on the control gate structure
108
, a voltage of+5 Volts is applied on the drain bit line junction
110
, and a voltage of 0 Volts (or a small bias of 0.25 Volts for example) is applied on the source bit line junction
114
and on the semiconductor substrate
103
. Alternatively, during erasing of the flash memory cell
100
, referring to
FIG. 2
, a voltage of−9.5 Volts is applied on the control gate structure
108
, a voltage of 0 Volts is applied on the drain bit line junction
110
, and a voltage of+4.5 Volts is applied on the source bit line junction
114
and on the semiconductor substrate
103
.
In any case of
FIGS. 1
or
2
, charge carriers are injected through the tunnel dielectric structure
102
and into the floating gate structure
104
. Such charge carriers may be from the channel region between the drain bit line junction
110
and the source bit line junction
114
in the semiconductor substrate
103
. Such voltage biases result in a large voltage difference of about 9V between the control gate structure
108
and the source bit line junction
114
during programming of the flash memory cell
100
and of about 14V between the control gate structure
108
and the source bit line junction
114
during erasing of the flash memory cell
100
. These relatively large voltage differences between the control gate structure
108
and the source bit line junction
114
may cause charge carriers to undesirably leak out of the floating gate structure
104
and to the source bit line junction
114
resulting in gate induced source leakage current since the floating gate structure
104
overlaps the source bit line junction
114
.
Furthermore, a voltage difference of about+5 Volts between the drain bit line junction
110
and the source bit line junction
114
may cause charge carriers from the gate induced source leakage current to migrate to the drain bit line junction
110
resulting in undesired bit line leakage current, especially when the drain bit line junction
110
and the source bit line junction
114
are situated relatively close together in a flash memory device having scaled down dimensions. The gate induced source leakage current and the bit line leakage current degrade the performance of the flash memory cell
100
.
Thus, a mechanism is desired for minimizing the gate induced source leakage current to enhance the performance of the flash memory cell.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, the overlap of the floating gate structure over the drain bit line junction and/or the source bit line junction is minimized to in turn minimize the gate induced source leakage current.
In one embodiment of the present invention, for fabricating a flash memory cell of an electrically programmable memory device on a semiconductor substrate, a layer of tunnel dielectric material is deposited on the semiconductor substrate, a layer of floating gate material is deposited on the layer of tunnel dielectric material, a layer of floating dielectric material is deposited on the layer of floating gate material, and a layer of control gate material is deposited on the floating dielectric material. A layer of patterning material is deposited and patterned on the layer of control gate material to form a patterning structure having a first length on the layer of control gate material. Any region of the layer of tunnel dielectric material, the layer of floating gate material, the layer of floating dielectric material, and the layer of control gate material not under the patterning structure is etched away to form a tunnel dielectric structure comprised of the tunnel dielectric material disposed under the patterning structure, to form a floating gate structure comprised of the floating gate material disposed under the patterning structure, to form a floating dielectric structure comprised of the floating dielectric material disposed under the patterning structure, and to form a control gate structure comprised of the control gate material disposed under the patterning structure.
In a general aspect of the present invention, the length of the floating gate structure is trimmed down from the first length of the patterning structure to a second length at an interface between the floating gate structure and the tunnel dielectric structure by etching away a portion of the floating gate material from at least one of a first sidewall and a second sidewall of the floating gate structure. A drain bit line junction of the flash memory cell is formed toward the first sidewall of the floating gate structure, and a source bit line junction of the flash memory cell is formed toward the second sidewall of the floating gate structure, by implanting a drain and source dopant into exposed regions of the semiconductor substrate. A thermal anneal is then performed such that the floating gate structure overlaps the drain bit line junction of the flash memory cell by being disposed over a portion of the drain bit line junction of the flash memory cell and such that the floating gate structure overlaps the source bit line junction of the flash me

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