Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-11
2004-10-26
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S424000, C438S542000, C438S593000, C438S761000
Reexamination Certificate
active
06808995
ABSTRACT:
DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention relates in general to a semiconductor device and, more particularly, to a semiconductor structure for minimizing and eliminating short-channel effects, and providing decreased bit line resistance.
2. Background of the Invention
Device characteristics of conventional metal-oxide-silicon field-effect transistors (MOSFETs), such as threshold voltage and subthreshold current, generally may be predicted through mathematical formulas. However, a trend in modern integrated circuit manufacture is to produce MOSFETs with reduced feature sizes, one such size being the channel length. As the channel length is reduced to the same dimension as the widths of the source and drain depletion regions of a MOSFET, some of the charges in the channel region may become linked to the charges in the source and/or drain depletion regions. As a result, the channel may become partially depleted, skewing the threshold voltage and other device characteristics of the MOSFET. This is known as short-channel effects.
A known phenomenon associated with the short-channel effects is the unintended injection of hot carriers. These unintended carriers are injected into the gate structure, altering the threshold voltage of the MOSFET. As the channel length decreases below 2 &mgr;m, the device characteristics become so influenced by the short-channel effects that they can no longer be accurately predicted through mathematical formulas.
A number of prior art devices have been proposed to address the short-channel effects. Some have proposed reducing the dimensions of the source and drain depletion regions. Such a reduction, however, has an unintended adverse effect of increasing bit line resistance.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a semiconductor device that includes a substrate having a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions, a conductor layer disposed over the substrate, wherein the conductor layer overlaps the source region, shallow trench isolation, and drain region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide, wherein the gate, source region, and drain region form a transistor.
In one aspect, the conductor layer electrically connects the source and drain regions to serve as the channel region of the transistor.
Also in accordance with the present invention, there is provided a semiconductor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions; a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region; a gate oxide disposed over the conductor layer; and a gate structure formed over the gate oxide, wherein the source region, drain region, and the gate structure form a transistor.
Additionally in accordance with the present invention, there is provided a semiconductor device that includes a first transistor including, a first diffused region, a second diffused region formed spaced apart from the first diffused region, a first shallow trench isolation disposed between and contiguous with the first and second diffused regions, wherein the first shallow trench isolation electrically isolates the first and second diffused regions, a first conductor layer formed over the first diffused region, the first shallow trench isolation, and the second diffused region, a first gate oxide disposed over the first conductor layer, and a first gate structure formed over the first gate oxide. There is also provided a second transistor formed adjacent the first transistor that includes a third diffused region formed spaced apart from the first diffused region, a fourth diffused region formed spaced apart from the third diffused region, a second shallow trench isolation disposed between and contiguous with the third and fourth diffused regions, and formed spaced apart from the first shallow trench isolation, wherein the second shallow trench isolation electrically isolates the third and fourth diffused regions, a second conductor layer formed spaced apart from the first conductor layer, and over the third diffused region, the second shallow trench isolation, and the fourth diffused region, a second gate oxide disposed over the second conductor layer, and a second gate structure formed over the second gate oxide.
In one aspect, the first and second diffused regions form the source and drain regions of the first transistor.
In another aspect, the second and third diffused regions are the same diffused region.
In yet another aspect, there additionally includes a third conductor layer formed contiguous with the first conductor layer and disposed over one of the first and second diffused regions, wherein the third conductor layer is doped with a same type of impurity as one of the first and second diffused regions.
Further in accordance with the present invention, there is provided a method for minimizing short-channel effects in a transistor that includes providing a substrate, providing a source region and a drain region in the substrate, providing a shallow trench isolation between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions, providing a conductor layer over the substrate, wherein the conductor layer overlaps the source region, shallow trench isolation, and drain region, providing a gate oxide over the conductor layer, and providing a gate structure over the gate oxide, wherein the gate structure, source region and drain region form a transistor.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.
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Wolf, S., “Short-Channel Effects and how They Impact MOS Processing”. Silicon Processing for the VLSI Era-Process Integration, pp. 338-367, vol. II, 1990.
Lai Han Chao
Lin Hung-Sui
Lu Tao Cheng
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Loke Steven
Macronix International Co. Ltd.
Magee Thomas
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