Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2003-01-13
2004-12-28
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C326S083000, C326S086000, C326S087000
Reexamination Certificate
active
06836143
ABSTRACT:
This nonprovisional patent application claims priority upon Korean Patent Application No. 2002-38821, filed on Jul. 5, 2002, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention is directed to a semiconductor integrated circuit device, and, in particular, a semiconductor integrated circuit device including a termination circuit for terminating a bus.
BACKGROUND OF THE INVENTION
As is well known, a bus used for signal transmission between different integrated circuit devices (e.g., one or more microprocessors, one or more chipsets, one or more memory controllers, one or more memories, one or more graphic controllers, etc.,) may be terminated through a termination resistor, which aids in the suppression of signal reflection as a result of an integrated circuit device acting as a receiver or transmitter. Signal reflection negatively affects signal integrity. This negative effect is even more evident in an integrated circuit device operating at high-speed. In order to suppress signal reflection as much as possible, a termination resistor may be installed on a bus that is placed at a closest position to the integrated circuit device.
Recently, there has become a greater desire for thinner and smaller non-memory products, such as microprocessors and Application Specific Integrated Circuits (ASICs). As a result of this desire, a ball grid array package, in which external pins are arranged at its bottom, has become a popular semiconductor package. A ball grid array type of a semiconductor integrated circuit package normally accepts Pin Grid Array (PGA) and flip chip concepts and reduces a space occupied by the semiconductor package as compared with a conventional Quad Flat Package (QFP). The ball grid array type of a semiconductor integrated circuit package also improves electric and thermal capacities and is more economical for multi-pin structures over 300 pins.
External terminals arranged at the package bottom may be electrically connected to bus lines. When the bus lines are terminated, external terminals that are arranged adjacent to the center of the package are arranged a relatively long distance from corresponding termination resistors as compared with external terminals that are arranged adjacent to edges of the package. Namely, a remaining bus line exists between an external terminal at a package center and a corresponding termination resistor. This arrangement results in signal reflection.
An example of an on-die termination structure is disclosed in U.S. Pat. No. 6,157,206 entitled “ON-CHIP TERMINATION”. A semiconductor integrated circuit device disclosed in the '206 patent includes an on-chip input buffer, a termination circuit, and an impedance control circuit. The termination circuit is included in the device and terminates a bus line connected to the input buffer. The impedance control circuit is connected to an external reference resistor, and controls impedance of the termination circuit so as to have the same value as the impedance of the external reference resistor.
In a case where a semiconductor integrated circuit device including an on-die termination circuit is mounted on a board where a bus is terminated, the on-die termination and impedance control circuits of the device may be controlled so as to be disabled. For example, the termination and impedance control circuits are disabled by applying an external command to the integrated circuit device via a separately provided pin or by programming a mode set circuit in the integrated circuit device. If the on-die termination and impedance control circuits of the integrated circuit device operate as described above, power may be unnecessarily consumed by the termination and impedance control circuit.
Although the '206 patent describes “on-chip termination”, similar problems may occur in “active termination” and “on-die termination” arrangements.
SUMMARY OF THE INVENTION
In an exemplary embodiment, the present invention is directed to a semiconductor integrated circuit device which is capable of reducing power consumption due to an impedance control circuit, without a separate pin or external command.
In another exemplary embodiment, the present invention is directed to a semiconductor integrated circuit device which is capable of controlling an operation of an impedance control circuit based on a connection state of an external reference resistor, without a separate pin or external command. In accordance with an exemplary embodiment, the present invention, is directed to a semiconductor integrated circuit that includes a termination circuit for terminating a bus line, an impedance control circuit for controlling an impedance of the termination circuit depending on an impedance of an external reference resistance, so as to have the same or substantially the same impedance as that of the external reference resistance, and a detection circuit for detecting whether the external reference resistance is electrically connected to the semiconductor integrated circuit and disabling the impedance control circuit depending on a detection result.
In another exemplary embodiment, the termination circuit is disabled when the impedance control circuit is disabled. The detection circuit is electrically connected to the external reference resistor, and activates a control signal for disabling the impedance control circuit when the external reference resistor is disconnected from the semiconductor integrated circuit.
In another exemplary embodiment, the impedance control circuit generates an impedance control code, which indicates an impedance value of the external reference resistor, depending on the impedance of the external reference resistor.
In another exemplary embodiment, the detection circuit activates a control signal for disabling the impedance control circuit when the impedance control code indicates that the external reference resistor is disconnected from the semiconductor integrated circuit.
In another exemplary embodiment, the present invention is directed to a detection circuit including a connection to a bonding pad of a semiconductor integrated circuit, and a circuit for detecting whether a reference resistance, external to the semiconductor integrated circuit, is electrically connected to the semiconductor integrated circuit and disabling an impedance control circuit of the semiconductor integrated circuit depending on a detection result.
In another exemplary embodiment, the circuit includes a reference current source, a current mirror connected to the reference current source and the bonding pad, and a comparator for comparing a voltage of the bonding pad with a reference voltage, the comparator generating a control signal for disabling impedance control circuit when the voltage of the bonding pad is higher than the reference voltage.
In another exemplary embodiment, the circuit includes an OR gate for receiving an impedance control signal from the impedance control circuit and outputting a disable signal.
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Harness & Dickey & Pierce P.L.C.
Nguyen Khai M.
Samsung Electronics Co,. Ltd.
Tokar Michael
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