Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-25
2004-10-05
Thomas, Tom (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S259000, C438S299000, C438S593000, C438S596000
Reexamination Certificate
active
06800526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for manufacturing flash memory integrated circuits, and more particularly to a method for manufacturing a self-aligned split-gate flash memory cell.
2. Description of the Prior Art
Conventional Erasable and Programmable Read-Only Memory (EPROM) devices have memory cells which comprise floating-gate transistors. A wide variety of EPROM is available. One form of EPROM is a flash EPROM.
Conventional flash memory devices have a split-gate structure comprised of one floating gate and one control gate. To form the floating and control gates, flash memory cells, however, are often bulky and have complex geometries of multiple gate layers. Therefore, it is difficult to fabricate a split-gate structure in a desired memory cell space.
Referring to
FIG. 1
, the conventional split-gate flash memory cell has a structure wherein the source/drain regions
11
and
12
are formed in a semiconductor substrate
10
, a gate insulating film
13
is formed on the substrate
10
, a floating gate
14
is formed on the gate insulating film
13
, and a control gate
16
is formed on the floating gate
14
. The control gate
16
and the floating gate
14
are insulated from each other by a dielectric film
15
, and the split gate of the flash memory cell is thus made.
The floating gate
14
is defined by the photolithographic process known to one of ordinary skill in the art. Unfortunately, it is often difficult to self-align and requires a larger size of memory cell. In addition, the channel length of the control gate
16
is determined during the process of forming the floating gate
14
. In this connection, in the case where a misalignment of a mask occurs during the photolithographic process forming the floating gate
14
, a desired channel length of the control gate
16
cannot be readily obtained.
FIGS. 2A
to
2
E illustrate the manufacturing sequences of a conventional split-gate flash memory device.
Referring to
FIG. 2A
, an insulating film
21
is formed on a semiconductor substrate
20
and is photo-etched to form openings
22
. Using the insulating film
21
as an ion-implantation blocking mask, n
+
-type impurity ions are implanted into the semiconductor substrate
20
, thereby forming source/drain regions
23
and
24
.
As shown in
FIG. 2B
, after removing the insulating film
21
, which serves as an ion-implantation blocking mask, a gate insulating film
25
is formed on the substrate
20
. Then, a polysilicon film
26
is formed on the gate insulating film
25
.
As shown in
FIG. 2C
, after coating the polysilicon film
26
with a photoresist film
27
, a photomask is aligned on the photoresist film
27
, and the polysilicon film
26
is photo-etched. As shown in
FIG. 2D
, floating gates
26
′ are thus formed.
As shown in
FIG. 2E
, a dielectric film
28
is formed on the surfaces of the floating gates
26
′, and a control gate
29
is formed over the entire surface of the substrate
20
, thereby obtaining the control split-gate flash memory device.
However, in a case where a photomask is misaligned, the channel length of the floating gates
26
′ is relatively increased or decreased. Therefore, the channel length of the split control gates
29
is decreased or increased.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a fixed space between the floating gates of the flash memory cell.
It is another object of the invention to provide the flash memory cell with a self-aligned split gate to reduce the size of the memory cell.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.
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patent: 5910912 (1999-06-01), Hsu et al.
patent: 5998263 (1999-12-01), Sekariapuram et al.
patent: 6054345 (2000-04-01), Alsmeier et al.
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patent: 6133098 (2000-10-01), Ogura et al.
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patent: 6352895 (2002-03-01), Lam
patent: 6420234 (2002-07-01), Park et al.
patent: 2002/0052079 (2002-05-01), Wen
patent: 2002/0102793 (2002-08-01), Wu
Huang Cheng-Chih
Huang Chung-Lin
Lin Chi-Hui
Nanya Technology Corporation
Richards N. Drew
Thomas Tom
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