Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-10-14
2004-10-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S055000, C365S066000, C365S171000, C365S189050, C365S189070, C365S189090, C365S193000
Reexamination Certificate
active
06807089
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for operating an MRAM semiconductor memory configuration having a multiplicity of TMR memory cells, which, in a memory cell array, are connected to bit lines at one of their ends and to word lines at their other end.
As is known, an MRAM semiconductor memory configuration is based on ferromagnetic storage with the aid of the TMR effect. Located at a crossover point of a word line and a bit line is a TMR memory cell having a layer stack containing a soft-magnetic layer, a tunneling resistance layer and a hard-magnetic layer. Generally, the magnetization direction of the hard-magnetic layer is predetermined, while the magnetization direction of the soft-magnetic layer is adjustable by sending corresponding currents in specific directions through the word line and the bit line. With these currents, the soft-magnetic layer can be magnetized in a parallel or anti-parallel fashion with respect to the hard-magnetic layer. In the case of parallel magnetization, the resistance of the layer stack is lower than in the case of anti-parallel magnetization, which can be evaluated as the logic state “0” and “1”, or vice versa. As an alternative, information can also be stored in the hard-magnetic layer, the soft-magnetic layer serving for the read-out. What is disadvantageous in this case, however, is that an increased write current is required for switching the magnetization of the hard-magnetic layer.
To date, essentially two architectures that differ from one another have been proposed for an MRAM semiconductor memory configuration.
In the so-called “crosspoint” construction, the individual TMR memory cells are located directly between mutually crossing interconnects which form bit and word lines. In the case of the crosspoint construction, no semiconductor components, and in particular no transistors, are required for the individual memory cells, so that a plurality of layers of TMR memory cells can readily be stacked one above the other. Very high integration densities can thus be achieved for an MRAM. However, in the case of such a “crosspoint” construction, parasitic currents inevitably flow via non-selected memory cells. Therefore, in large memory cell arrays, the individual TMR memory cells have to be furnished with a very high resistance in order that the parasitic currents can be kept low. The read operation is relatively slow on account of the high resistance of the individual TMR memory cells.
In the case of the other architecture, a switching or selection transistor is additionally assigned to each individual TMR memory cell with the above-mentioned layer stack (in this respect, see the reference by M. Durlam: entitled “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”).
The accompanying
FIG. 1
shows diagrammatically and in perspective a section from four TMR memory cells TMR
1
, TMR
2
, TMR
5
, TMR
6
, which are respectively assigned a selection transistor TR
11
, TR
12
, TR
21
, TR
22
. As mentioned, each TMR memory cell contains a layer stack of the hard-magnetic layer
11
, the tunneling resistance layer
12
and the soft-magnetic layer
13
. Bit lines BL
1
and BL
2
form interconnects above the soft-magnetic layer
13
and are directly connected to the latter. Data or digit lines DL
1
are disposed below the hard-magnetic layer
11
in a direction that crosses the bit lines BL
1
, BL
2
and are connected to the layer. The selection transistor TR
11
, TR
12
, TR
21
and TR
22
, whose gates are connected to word lines WL
1
and WL
2
, is coupled to each TMR memory cell.
An MRAM semiconductor memory configuration having TMR memory cells that are connected to such switching transistors is distinguished by the fact that parasitic currents are practically precluded. As a result, even in large memory cell arrays, the memory cells can be provided with a lower resistance of the TMR element. Moreover, the reading method is simplified, thereby enabling a faster access than in the case of the “crosspoint” construction. However, the construction with transistor/TMR memory cells has the disadvantage that the dimensions are considerably larger compared with the crosspoint construction. In addition, it is not possible to perform direct stacking of TMR cell planes since a transistor and thus a silicon surface is required for each memory cell of a memory cell array.
In an earlier patent application, the present applicant proposed an MRAM memory configuration in which the advantages of a “crosspoint” construction are largely combined with the advantages of transistor/TMR memory cells.
The accompanying
FIG. 2
shows such an MRAM semiconductor memory configuration that combines a cross-point construction with a transistor/TMR memory cell construction. In this case, groups each containing a plurality of TMR memory cells are formed. The TMR memory cells TMR
1
, TMR
2
, TMR
3
and TMR
4
of a group are in each case jointly connected to a bit line BL by one of their ends and are jointly connected to a selection transistor TR
1
at their other end, the word line
1
being connected to the gate of the transistor. In a further TMR memory cell group, likewise a plurality of TMR memory cells, for example four TMR memory cells TMR
5
, TMR
6
, TMR
7
and TMR
8
, are jointly connected to the same bit line BL by one of their ends and are jointly connected to a second selection transistor TR
2
by their other end, a second word line WL
2
being connected to the gate terminal of the transistor TR
2
. In the case of the MRAM semiconductor memory configuration shown in
FIG. 2
, the space requirement for the transistors TR
1
, TR
2
can be considerably reduced by virtue of the assignment of only one switching or selection transistor TR
1
, TR
2
to in each case a plurality of TMR memory cells, for example four TMR memory cells, with the result that such an MRAM semiconductor memory configuration allows an increased packing density in the memory cell array.
Generally, there is the problem in MRAM semiconductor memory configurations that the reproducibility or the distribution of the resistances of the TMR memory cells can be realized inaccurately or can be unbalanced, since the resistances of the TMR memory cells depend extremely sensitively (exponentially) on the barrier thickness, i.e. the thickness of the tunnel layer. This makes it more difficult to realize an expedient reference for evaluation of the read signal. Essentially two possibilities have been discussed heretofore for solving this problem.
An external reference (reference cell or reference current/voltage source) is provided. For this, the TMR swing must be significantly larger than the fluctuations of the resistances. This method would be impossible for a memory configuration with a plurality of parallel TMR memory cells per transistor as described above.
During destructive reading, the TMR memory cell is subjected to rewriting after reading in a specific direction and thus compared; writing-back subsequently has to be effected. In this case, the memory cell itself serves as a reference, so that resistance fluctuations in the memory cell are unimportant. However, the method is time-consuming and leads to data alterations if the reading method is not 100% reliable. Since writing has to be effected more frequently, reliability problems can arise.
The reference by Wang et al.: entitled “Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory”, IEEE Transactions on Magnetics, Vol. 33, No. 6, Nov. 1997, pp. 4498-4512, discloses a method for operating an MRAM semiconductor memory configuration having a multiplicity of TMR memory cells, which, in a memory cell array, are connected to bit lines at one of their ends and to word lines at their other end. The magnetization of the soft-magnetic layer is situated in a first direction parallel to the easy magnetization axis, and afterward, by a current pulse through the electrically non-connected write line, the magnetization direction of the soft-magnetic layer is brought into a second direction
Gogl Dietmar
Schloesser Till
Nelms David
Pham Ly Duy
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