Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-01-29
2004-02-24
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06697981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology for evaluating the location of a failure in a logic circuit. More particularly, the invention relates to a system, a method, a device, and a recording medium for evaluating the location of a failure, which are suitably used for the evaluation of the location of a failure in a logic circuit including gates defined in a hierarchical manner.
2. Description of the Related Art
A system for evaluating the location of a failure is designed to evaluate a path possibly having a failure propagated therethrough, which may satisfy an output pattern including a failure output, and then evaluates a location of the failure based on such information. For example, as described in Japanese Patent Laid-Open Hei 08 (1996)-146093 (Patent No. 2655105), Japanese Patent Laid-Open Hei 10 (1998)-062494, and so on, this system can be used as a part of the failure location evaluating system of a sequential circuit. A technology described in each of such publications provides a system for evaluating the location of a failure, which is based on a path tracing method for evaluating a failure propagation path from a failure output terminal in an input direction.
In the case of evaluating a failure propagation path, it is necessary to obtain a logical state for each of the nodes (a gate, a signal line, and a terminal) inside a circuit. Here, description will be made with reference to a specific circuit.
FIG. 18
shows a benchmark circuit C
17
composed only of NAND gates. Hereinbelow, with respect to the circuit shown in
FIG. 18
, a method for evaluating a failure propagation path with L
22
=1 and L
23
=1 is described based on a method for extracting a failure propagation path, which the inventor of the present invention disclosed in Japanese Patent Laid-Open Hei 11 (1999)-153646. In
FIG. 18
, a parenthesized numeral denotes an expected value of each signal line.
First, since there is no signal line state implied by L
22
=1 and L
23
=1, a signal line is retrieved to set a temporary logical value. According to the failure propagation path extracting method of the foregoing publication of Japanese Patent Laid-Open Hei 11 (1999)-153646, a temporary logical value is set on an input signal line of a gate connected to a failure signal line, a state of the gate having yet to be unestablished (unestablished gate).
FIG. 20
shows an IF-THEN operation (implication operation) in the input/output direction of a two-input NAND gate. When a logical value of an output signal line is “1”, and both of two logical values of the input signal lines are “X”, a logical value of either one of the input signal lines should be “0”. However, since it has yet to be established, the gate is determined to be an unestablished gate.
In the example shown in
FIG. 18
, a logical value “0” is temporarily set on L
16
, which is one of the input signal lines of a gate G
23
connected to the failure signal line L
23
. With L
16
=0 being temporarily set, L
2
=1 and L
11
=1 are implicated by the IFTHEN operation of G
16
. Thereafter, the IF-THEN operation and the temporary setting of a logical value are repeated and, by temporarily setting logical values on the signal lines of two locations, three logical states are obtained as shown in the decision tree of FIG.
19
. The obtained logical states inside the circuit describe the logical values of the respective signal lines in portions enclosed with squares of
FIG. 19
in the order of (L
1
, L
2
, L
3
, L
6
, L
7
, L
10
, L
11
, L
16
, L
19
, L
22
, and L
23
). The underline below each logical value represents a failure propagation path, in which an expected value is different from the logical value.
Each signal line on the failure propagation path obtained by the foregoing method becomes a failure location candidate, which is an origin for propagating a failure state to the failure output of the logic circuit.
The foregoing publications of Japanese Patent Laid-Open Hei 08 (1996)-146093, and Patent Laid-Open Hei 10 (1998)-062494 disclose the method of deciding a priority order among a failure candidates by weighting a failure propagation path evaluated according to a rule. One example is given hereinbelow. It is assumed for example that a failure propagation path like that shown in
FIG. 21
has been obtained. In this case, by calculating the number of failure output terminals as a weight, to which an error state may propagate, the parenthesized numerals are obtained as shown in
FIG. 21
when a failure is present in each path.
This weight can be obtained by transmitting the information about a failure output terminal in an input direction. On a path p
1
, there is a possibility of propagating failures to four failure output terminals (F
1
to F
4
), and a weight becomes a maximum value 4. Accordingly, it can be determined that the possibility of a failure present in the path p
1
is high.
As can be understood from the foregoing, the following three processings must be carried out for each gate with regard to the process for evaluating the location of a failure based on path tracing:
(1) an IF-THEN operation in an input/output direction based on the function of each gate;
(2) determination of an unestablished gate, and retrieval of a signal line, a temporary logical value being set thereon; and
(3) transmission of information regarding a related failure output terminal to the input side.
It has conventionally been considered that when the location of a failure is evaluated based on path tracing by setting a logic circuit including a user-defined gate serving as a target, the user must prepare a database for each gate for realizing the above three processings, and incorporate the database in a system. For such a user-defined gate, a hierarchical circuitry for logic simulation has been prepared, whereas no databases, in which process for evaluating a failure location is defines, have not.
Consequently, when the number of user-defined gates is increased, the number of databases to be prepared becomes enormous, as a result, a great deal of time and labor are required. In addition, as in the case of a flip-flop (FF), complicated processing must be taken into consideration, where the logical state of an input/output terminal is extending over time points. Accordingly the preparation of databases by a failure analyzer, not a designer, is difficult.
In a circuit designing environment, for the user-defined gate, a hierarchical circuitry is described based on a hardware descriptive language such as Verilog or the like by a basic gate such as an AND, a NAND or the like to be evaluated, and kept in a library form. Thus, even those who are not circuit designers can carry out logic simulation.
Gate processing in the logic simulation can be realized only by an IF-THEN operation in an output direction. This is because a gate output logical state is uniquely set when a logical value of a gate input terminal is decided. However, determination of an unestablished gate necessary for the evaluation of a failure location, or transmission of information regarding a related failure output terminal cannot be realized only by such an IF-THEN operation in an output direction.
As is apparent from the foregoing, the following problems are inherent in the conventional a failure evaluating system.
A first problem is that a database dedicated to the process of evaluating the location of a failure needs to be created in the case of evaluating the location of a failure in the logic circuit including gates defined in a hierarchical manner.
This is because in the processing of each of the hierarchically defined gates for the evaluation of the location of a failure, the IF-THEN operation in the input/output direction, the retrieval of a signal line, a temporary logical value being set thereon, and the transmission of information regarding a failure terminal are essential, and only a database for a basic gate is prepared in the failure location evaluating device.
A second problem is th
Dildine R. Stephen
NEC Corporation
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