Self-aligned contacts to gates

Details Self-aligned contacts to gates Self-aligned contacts to gates

2002-08-22

2004-02-03

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S595000, C438S596000

Reexamination Certificate

active

06686247

ABSTRACT:

BACKGROUND
1. Field
Embodiments of the invention relate to circuit devices and the manufacture of device contacts.
2. Background
Access to and operation of devices (e.g., transistors, resistors, capacitors) on a substrate, such as circuit devices on a semiconductor (e.g., silicon) substrate is provided by contacts to the devices. During manufacture or forming of, for example, Metal Oxide Semiconductor (MOS) transistor semiconductor devices, it is important to assure gate contacts are not electrically short circuited (“shorted”) to junction regions (e.g., doped or source/drain region) within an active area. As a consequence, current techniques require placement of gate contacts to be spaced a distance away from active regions to avoid shorting to adjacent source/drains. For example, polysilicon gate contacts for memory cells (e.g., Static Random Access Memory (SRAM) or flash memory) are formed over the field region because gate electrodes are so narrow that a minor contact mask mis-alignment in the active region may result in shorting the gate contact to a source/drain.
What is needed is a technique for making contact to polysilicon gate layers on top of memory cell active regions, without restriction of proximity to source-drains regions.


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