Method of forming field effect transistor comprising at...

Details Method of forming field effect transistor comprising at... Method of forming field effect transistor comprising at...

2002-01-31

2004-12-14

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S595000

Reexamination Certificate

active

06830975

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming field effect transistors, including floating gate transistors.
BACKGROUND OF THE INVENTION
Memory is but one type of integrated circuitry. Some memory circuitry allows for both on-demand data storage and data retrieval. For example, memories which allow both writing and reading, and whose memory cells can be accessed in a random order independent of physical location, are referred to as random-access memories (RAM). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. Entering data into a read-only memory is typically referred to as programming, and the operation is considerably slower than the writing operation utilized in random-access memory. With random-access memory, information is typically stored with respect to each memory cell either through charging of a capacitor or the setting of a state of a bi-stable flip-flop circuit. With either, the stored information is destroyed when power is interrupted. Read-only memories are typically non-volatile, with the data being entered during manufacturing or subsequently during programming.
Some read-only memory devices can be erased as well as written to by a programmer. Erasable read-only memory typically depends on the long-term retention of electronic charge as the information storage mechanism. The charge is typically stored on a floating semiconductive gate, such as polysilicon. One type of read-only memory comprises FLASH memory. Such memory can be selectively erased rapidly through the use of an electrical erase signal.
A FLASH memory cell typically comprises a single floating gate transistor. For multiple storage cells, such as used in large semiconductor memories, the storage cells of the memory are arranged in an array of rows and columns. The rows are typically considered as comprising individual conductive gate lines formed as a series of spaced floating gates received along a single conductive line (hereafter referred to as “a line of floating gates”). Source and drain regions of the cells are formed relative to active area of a semiconductor substrate, with the active areas being generally formed in lines running substantially perpendicular to the lines of floating gates. The sources and drains are formed on opposing sides of the lines of floating gates within the active area with respect to each floating gate of the array. Thus, lines (rows) of programmable transistors are formed.
One method of forming a floating gate construction is as follows. A gate dielectric layer is formed over semiconductive material. A floating gate layer, for example conductively doped polysilicon, is formed over the gate dielectric layer. Another gate dielectric layer is formed over the conductively doped polysilicon layer. An example construction includes three layers, for example comprising silicon oxide, silicon nitride and silicon oxide. Control gate material is formed thereover. Such might include conductively doped semiconductive material having a higher conductive metal or metal compound layer formed thereover. Typically, an insulating capping layer is formed over the conductive metal or metal compound layer. The floating gate layer is typically partially patterned prior to the provision of the control gate layer thereover such that discrete floating gates will ultimately be provided in the elongated floating gate line construction being formed. After forming the insulating capping layer, the entire construction is thereafter patterned, typically by subtractive etching, to form a desired elongated floating gate line. Source/drain implants are thereafter typically conducted.
In most applications, the substrate is ultimately oxidized to repair source/drain damage from the diffusion or other implant of impurities therein, and also effective to oxidize the sidewalls of at least the semiconductive material of the floating gate and control gate. This typically creates silicon dioxide bulges on the sidewalls of such material.
In certain circumstances where, for example, the metal or metal compound portion of the control gate material is predominantly tungsten, projecting filaments or dendrite-like projections can form from the tungsten, which is undesirable. The following invention was motivated in addressing the above issues, although such is in no way so limited. Methodical aspects of the invention are seen to have applicability to any integrated circuitry and in the fabrication of any field effect transistor, unless a claim is otherwise literally limited. The invention is limited only by the accompanying claims as literally worded without limiting reference to the specification, and in accordance with the doctrine of equivalents.
SUMMARY
The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.


REFERENCES:
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patent: 5691212 (1997-11-01), Tsai et al.
patent: 6033963 (2000-03-01), Huang et al.
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Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 4th ed., 2000, McGraw Hill, New York, pp. 303-305, 401-402.

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