Floating gate memory fabrication methods comprising a field...

Details Floating gate memory fabrication methods comprising a field... Floating gate memory fabrication methods comprising a field...

2002-10-01

2004-06-01

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S266000

Reexamination Certificate

active

06743675

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to floating gate nonvolatile memories.
A floating gate nonvolatile memory cell stores information by storing an electrical charge on its floating gate. The floating gate is capacitively coupled to the control gate. In order to write the cell, a potential difference is created between the control gate and some other region, for example, the source, drain or channel region of the cell. The voltage on the control gate is capacitively coupled to the floating gate, so a potential difference appears between the floating gate and the source, drain or channel region. This potential difference is used to change the charge on the floating gate.
In order to reduce the potential difference that has to be provided between the control gate and the source, drain or channel region, it is desirable to increase the capacitance between the control and floating gates relative to the capacitance between the floating gate and the source, drain or channel region. More particularly, it is desirable to increase the “gate coupling ratio” GCR defined as CCG/(CCG+CSDC) where CCG is the capacitance between the control and floating gates and CSDC is the capacitance between the floating gate and the source, drain or channel region. One method for increasing this ratio is to form spacers on the floating gate. See U.S. Pat. No. 6,200,856 issued Mar. 13, 2001 to Chen, entitled “Method of Fabricating Self-Aligned Stacked Gate Flash Memory Cell”, incorporated herein by reference. In that patent, the memory is fabricated as follows. Silicon substrate
104
(
FIG. 1
) is oxidized to form a pad oxide layer
110
. Silicon nitride
120
is formed on oxide
110
and patterned to define isolation trenches
130
. Oxide
110
and substrate
104
are etched, and the trenches are formed. Dielectric
210
(FIG.
2
), for example, borophosphosilicate glass, is deposited over the structure to fill the trenches, and is planarized by chemical mechanical polishing (CMP). The top surface of dielectric
210
becomes even with the top surface of nitride
120
. Then nitride
120
is removed (FIG.
3
). Oxide
110
is also removed, and gate oxide
310
is thermally grown on substrate
104
between the isolation trenches. Doped polysilicon layer
410
.
1
(
FIG. 4
) is deposited over the structure to fill the recessed areas between the isolation regions
210
. Layer
410
.
1
is polished by chemical mechanical polishing so that the top surface of layer
410
.
1
becomes even with the top surface of dielectric
210
.
Dielectric
210
is etched to partially expose the “edges” of polysilicon layer
410
.
1
(FIG.
5
). Then doped polysilicon
410
.
2
(
FIG. 6
) is deposited and etched anisotropically to form spacers on the edges of polysilicon
410
.
1
. Layers
410
.
1
,
410
.
2
provide the floating gates.
As shown in
FIG. 7
, dielectric
710
(oxide
itride/oxide) is formed on polysilicon
410
.
1
,
410
.
2
. Doped polysilicon layer
720
is deposited on dielectric
710
and patterned to provide the control gates.
Spacers
410
.
2
increase the capacitance between the floating and control gates by more than the capacitance between the floating gates and substrate
104
, so the gate coupling ratio is increased.
SUMMARY
This section is a brief summary of some features of the invention. The invention is defined by the appended claims which are incorporated into this section by reference.
In some embodiments of the present invention, before the floating gate polysilicon is deposited, the trench dielectric
210
is subjected to an etch which includes a horizontal etch component. For example, a wet etch can be used. Consequently, the sidewalls of dielectric
210
become recessed away from the active areas (see
FIG. 13
for example). Therefore, the floating gate polysilicon
410
is wider at the top (FIG.
14
). The gate coupling ratio is therefore increased.
The invention is not limited to polysilicon, silicon oxide, or other particular materials, or to particular dimensions, memory structures, or fabrication processes. Other features are described below.


REFERENCES:
patent: 5940717 (1999-08-01), Rengarajan et al.
patent: 6127215 (2000-10-01), Joachim et al.
patent: 6130129 (2000-10-01), Chen
patent: 6200856 (2001-03-01), Chen
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6228713 (2001-05-01), Pradeep et al.
patent: 6319794 (2001-11-01), Akatsu et al.
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patent: 6417047 (2002-07-01), Isobe
patent: 6448606 (2002-09-01), Yu et al.
patent: 6518618 (2003-02-01), Fazio et al.
patent: 2000-174242 (2000-06-01), None
U.S. patent application No. 10/266,378 entitled “Floating Gate Memory Structures And Fabrication Methods,” filed on Oct. 7, 2002, Inventor: Chia-Shun Hsiao.
Patent Abstracts of Japan of JP 2000-174242.
Aritome, S. et al., “A 0.67um2Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) For 3V-only 256Mbit NAND EEPROMs,” International Electron Devices meeting 1994, San Francisco, CA, Dec. 11-14, 1994, pp. 94-61-94-64.
Keeney, Stephen N., A 130nm Generation High Density Etox™ Flash Memory Technology, Intel, Corporation, Santa Clara, California, USA, 42 sheets.
Silicon, Flash and Other Non-Volatile Memory Technologies, Sep. 12, 2002, pp. 1-4.

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