Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-10-30
2004-10-19
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S197000
Reexamination Certificate
active
06806141
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to field effect transistors (FETs). More particularly, this invention pertains to a field effect transistor having an elongated conductive channel that is inclined with respect to the upper surface of an etched substrate.
2. Description of the Prior Art
Many proposals have been made for making field effect transistors in silicon nanowires. Elongated nanowires of silicon are characterized by diameters on the order of 5 to 30 nanometers, substantially smaller than conventional integrated circuits that include devices having corresponding dimensions on the order of 100 nanometers or more.
Efficient modulation of the conductance of the channel region of a nanowire FET requires that the channel region of the nanowire be only moderately doped while the regions external to the active channel (source and drain) should be heavily doped to reduce series resistance. (Generally, a “heavily doped” region is understood by those skilled in the art to be characterized by a sufficient amount of doping to produce a resistivity value of 0.01 ohm-cm or less (conductivity of 100 (ohm-cm)
−1
or more.)
Unfortunately, it has been found to be relatively difficult to control absolute dimensions and tolerances at the level of 100 nm or less by conventional lithography processes. In many proposed devices, for example, the distances between the heavily doped regions of the nanowire (if heavily doped regions are employed) and the channel are not well controlled. This leads to high and variable series resistance and/or to regions of abnormally high electric field.
SUMMARY OF THE INVENTION
The preceding and other shortcomings of the prior art are addressed by the present invention that provides, in a first aspect, a field effect transistor. Such transistor includes a substrate having a substantially-planar upper substrate surface. An elongated channel of semiconductor material is inclined with respect to the upper substrate surface. The channel includes a top and a bottom with the bottom of the channel contacting the upper substrate surface.
The substrate is substantially conductive in the region contacting the bottom of the elongated channel. The channel includes a heavily doped region adjacent the top thereof. A gate comprises a planar layer of conductive material arranged substantially parallel to the upper substrate surface.
In a second aspect, the invention provides a method for forming a field effect transistor. Such method is begun by providing a conductive substrate. The substrate is then etched to form an upstanding pillar adjacent a substantially-planar upper surface of the etched substrate.
A stack is then formed adjacent the pillar. The stack is of substantially-planar layers of material that include a first insulator layer adjacent the upper surface of the etched substrate, a gate layer of conductive material overlying the first insulator layer and a second insulator layer overlying the gate layer.
The pillar is then etched to the level of the substantially-planar upper surface of the etched substrate to form an upstanding pore within the stack. A gate insulator layer is then formed at the interior of the upstanding pore.
An upstanding channel of semiconductor material is then formed interior of the gate insulator layer having a top region and a bottom region. Finally, the top region of the upstanding channel is heavily doped.
In a third aspect, the invention provides a method for forming a field effect transistor that is begun by providing a substrate of semiconductor material. Such substrate is then etched to form an upstanding pillar adjacent a substantially-planar upper surface of the etched substrate.
A conductively-doped region is then formed within the etched substrate substantially and immediately beneath the pillar. A stack is then formed adjacent the pillar of substantially-planar layers of material comprising a first insulator layer adjacent the upper surface of the etched substrate, a gate layer of conductive material overlying the first insulator layer and a second insulator layer overlying the gate layer.
The pillar is then etched to the level of the substantially-planar upper surface of the etched substrate to form an upstanding pore within the stack. A gate insulator layer is then formed interior to the upstanding pore. An upstanding channel of semiconductor material having a top region and a bottom region is then formed interior of the gate insulator layer. Finally, the top region is then heavily doped.
In a fourth aspect, the invention provides a method for forming a field effect transistor. The method is begun by providing a substrate having an upper surface. A stack of substantially-planar layers of material is then formed on the substrate. Such stack comprises a first insulator layer adjacent the upper surface of the substrate, a gate layer of conductive material overlying the first insulator layer and a second insulator layer overlying the gate layer.
An overlayer is then formed on top of the second insulator layer. The overlayer is then masked with a nanoparticle, then directionally etched to form an upstanding nanopillar on top of the second insulator layer.
A second overlayer is then deposited on top of the second insulator layer and the upstanding nanopillar. The second overlayer is then removed to the top of the upstanding nanopillar and the nanopillar is then removed to leave an upper nanopore within the second overlayer defining an etch mask.
A lower nanopore is directionally etched through the stack of materials to the upper surface of the substrate. The second overlayer is then removed and a gate insulator layer is then formed at the interior of the upstanding lower nanopore. An upstanding channel of semiconductor material is then formed interior of the gate insulator layer having a top region and a bottom region. Finally, the top region of the upstanding channel is heavily doped.
The preceding and other features and advantages of the present invention will become apparent from the detailed description that follows. Such description is accompanied by a set of drawing figures. Numerals of the drawing figures, corresponding to those of the written text, point to the features of the invention with like numerals referring to line features throughout both the written text and the drawing figures.
REFERENCES:
patent: 6614069 (2003-09-01), Rosner et al.
Hewlett--Packard Development Company, L.P.
Smith Bradley
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