Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-24
2004-08-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C257S329000, C257S330000
Reexamination Certificate
active
06770535
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for manufacture of a semiconductor integrated circuit device and to a semiconductor integrated circuit device technology. In particular, the invention relates to a process for manufacture of a semiconductor integrated circuit device having capacitor elements for information storage and to a technology which is effective in the application of such a semiconductor integrated circuit device.
A typical example of a semiconductor integrated circuit device having capacitor elements for information storage is a DRAM (Dynamic Random Access Memory). A memory cell of a DRAM is formed of one transistor, for memory cell selection, and a capacitor (an element for information storage) which is directly connected thereto; and, therefore, the DRAM is widely used as the main memory of a variety of computers, which require a large capacity memory, and for communication apparatuses, because the integrity is high and the price per unit per bit can be inexpensive. Since a capacitor is used for an element for information storage, however, in the case that it is left as it is, a signal charge used for information storage leaks as time elapses so that the storage content is eventually lost. Therefore, in a DRAM, a so-called refreshing operation, which periodically reproduces the storage content, is required in order to maintain the information of the memory cell. Therefore, in a semiconductor integrated circuit device having a DRAM, a variety of research and substantial technological development concerning the structure and circuit arrangement have been carried out in an attempt to increase the operation speed of the entire DRAM and to increase the refreshing characteristics. As for the technology for increasing the refreshing characteristics, since the refreshing characteristics are in inverse proportion to the junction electric field intensity in the semiconductor regions for sources and drains of the transistors for memory cell selection, the optimization of the impurity concentration diffusion in the semiconductor regions for the sources and drains has been developed so as to increase the refreshing characteristics by reducing the above junction electric field intensity.
For example, in the Japanese patent Laid-Open No. 61486/1994 (U.S. Pat. No. 5,426,326), a technology is described wherein contact holes are opened in an interlayer insulating film which covers MOS (Metal Oxide Semiconductor) transistors for memory cell selection in a DRAM memory cell so that the semiconductor regions for the sources and drains are exposed, and, after that, impurities for electric field relaxation are introduced beneath the semiconductor regions for the sources and drains through the above contact holes. In addition, for example, in the Japanese patent Laid-Open No. 359842/1998, a technology is disclosed wherein impurities (boron, or the like) for controlling the threshold voltage Vth of the MOS transistors for memory cell selection are implanted only on the side to which bit lines are connected in the semiconductor substrate so as not to be implanted on the capacitor side, and, thereby, the impurity (boron, or the like) concentration of the semiconductor substrate on the capacitor side is lowered so as to lower the junction electric field intensity in the semiconductor substrate on the capacitor side.
SUMMARY OF THE INVENTION
The present inventors have, however, found that the above described technologies have the following problems.
That is to say, as the miniaturization of elements proceeds, the impurity concentration in a semiconductor substrate with respect to, for example, the element dimension is enhanced, and the side wall insulating film formed on the side walls of the gate electrodes becomes thinner, so that the gate electrodes and the semiconductor regions (high impurity concentration regions) for the sources and drains become closer in distance; and, thereby, the above described junction electric field intensity becomes larger, and, as a result, a problem arises in that the deterioration of the refreshing characteristics cannot be prevented even in the case of the use of conventional technologies. Though, in a conventional DRAM, the power consumption has been limited in order to lengthen the refreshing time when the integration is heightened, the refreshing time cannot help but be made shorter since the junction electric field intensity becomes larger when the miniaturization of the element progresses to a higher integration. As a result of this, a problem arises in that, in the case where integration continues to be heightened at the present rate, the increase in the power consumption cannot be avoided.
An object of the present invention is to provide a technology which can reduce the junction electric field intensity in the semiconductor regions for the sources and drains of field effect transistors.
Another object of the present invention is to provide a technology which can increase the driving performance of field effect transistors.
Still another object of the present invention is to provide a technology which can increase the refreshing characteristics of a semiconductor integrated circuit device.
Yet another object of the present invention is to provide a technology which can reduce power consumption of a semiconductor integrated circuit device.
Still another object of the present invention is to provide a technology which can increase the element integrity of a semiconductor integrated circuit device.
A further object of the present invention is to provide a technology which can increase the reliability of a semiconductor integrated circuit device.
An additional object of the present invention is to provide a technology which can increase the yield of a semiconductor integrated circuit device.
The above described, as well as other, objects and novel characteristics of the present invention will be clarified through the description provided in this specification and the attached drawings.
A summary of a representative aspect of the invention which is disclosed in the present application will be briefly described as follows.
That is to say, the present invention provides the step of forming first trenches in a semiconductor substrate, the step of forming isolation parts by filling in said first trenches with an insulating film, the step of forming trenches for forming wires so as to overlap, in a plane manner, said isolation parts and active regions which are surrounded by said isolation parts, the step of forming an isolation film inside the trenches for forming said wires and the step of forming wires inside of said trenches for forming wires via said isolation film inside trenches, wherein in said step of forming trenches for forming wires, the corners of the bottom are rounded, and in said step of forming an isolation film inside the trenches part of, or all of, the insulating film is formed inside of the trenches through a deposition method.
In addition, the present invention provides the step of forming first trenches in a semiconductor substrate, the step of forming isolation parts by filling in said first trenches with an insulating film, the step of forming a mask having aperture parts including part of, both, of said isolation parts and active regions surrounded by said isolation parts on the semiconductor substrate, the step of forming third trenches by forming second trenches by removing the insulating film of the isolation parts which are exposed from said aperture parts and, after that, by removing the semiconductor substrate part which is exposed from said aperture parts, and the step of forming wires inside said second and third trenches.
In addition, the present invention provides first trenches formed in a semiconductor substrate, isolation parts formed by filling in said trenches with an insulating film, trenches for forming wires formed so as to overlap, in a plane manner, said isolation parts and active regions which are surrounded, in a plane manner, by said isolation parts, an insulating film inside th
Kimura Shin'ichiro
Oyu Kiyonori
Yamada Satoru
Kennedy Jennifer M.
Niebling John F.
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