Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-30
2004-08-17
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S227000, C438S224000, C438S185000
Reexamination Certificate
active
06777280
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor circuits, and more particularly to wells used in semiconductor circuits.
Some semiconductor circuits use wells biased at a predetermined voltage to obtain needed functionality or performance characteristics. For example, biased wells can be used to isolate transistors from each other. Thus, in some dynamic random access memories (DRAMs), NMOS transistors of DRAM cells are formed in a P-well formed in a biased deep N well (DNW) that isolates the P well from the P doped substrate. The P well itself is biased at a lower voltage than the substrate. Hence, the body regions of DRAM cell transistors in the P well are biased at a lower voltage than the body regions of NMOS transistors of read/write circuitry (for example, of sense amplifiers) that are fabricated in the substrate. The lower bias voltage in the P well reduces the leakage current through the DRAM cell transistors. The leakage current through these transistors is of concern because it could discharge the cells. At the same time, the lower bias voltage is not suitable for read/write NMOS transistors because the lower bias voltage would make these transistors slower. (Of note, the leakage current is not as big a concern for the read/write transistors as for the DRAM cell transistors.) The biased DNW isolates the DRAM cell transistors from the read/write transistors.
In order to improve the electrical contact between a voltage source biasing the DNW and the DNW itself, the DNW is provided with a low-resistance, heavily-doped N+ contact region located at the substrate surface. The N+ contact region is formed in a separate N well which itself is formed in the DNW. The reason for the separate N well is as follows.
One of the DRAM fabrications steps is a channel stop implant. The channel stop implant is a P-type implant performed into the NMOS transistor active areas and into field isolation regions. The purpose of the channel stop implant is to increase the punch-through voltages of NMOS transistors and the punch-through and threshold voltages of parasitic field transistors. The channel stop implant is blocked from N wells in which PMOS transistors are formed. To simplify mask generation, the mask for the channel stop implant is made to be a reverse of the mask used for the N-type implant that creates the N wells. Thus, the channel stop implant is implanted precisely into those areas which are blocked from the N-well implant.
Besides the N wells containing the PMOS transistors, the channel stop implant is also blocked from the N+ contact region used to bias the DNW. This is done to prevent the channel stop P-type dopant from impeding electrical contact between the N+ contact region and the DNW. In order to enable the channel stop implant mask to be the reverse of the N well mask and still to block the channel stop implant from the N+ contact region, the N+ contact region is formed in the separate N well which is formed with the same N well mask as used for the N wells containing the PMOS transistors.
It is desirable to reduce spacings associated with wells in the integrated circuit. Of note, a minimal spacing is typically required between a well and transistors outside the well. For example, in DRAMs a minimal spacing is required between the DNW and read/write circuitry transistors. It is desirable to reduce such spacings.
SUMMARY OF THE INVENTION
According to the present invention, integrated circuit spacing requirements are reduced. In some embodiments, spacing requirements between wells and transistors outside the wells are eliminated. Therefore, the integrated circuit size can be reduced.
More particularly, in some embodiments, the separate N wells containing the N+ contact regions in the DNWs are eliminated. This is made possible by modifying the channel stop mask not to be a reverse of the N well mask.
Further, spacing requirements between wells and transistors outside the wells are eliminated as follows. When transistors outside the well (e.g., a DNW) are laid out, the transistor placed adjacent to the well is a transistor that can be used to bias the well. This transistor couples a predetermined voltage from one of its electrodes to the other. For example, in a DRAM, this transistor can be a precharge transistor that couples a predetermined voltage to a bit line to precharge the bit line before a memory access (e.g., a memory read operation). The predetermined voltage is also suitable to bias the well. The transistor electrode that receives the predetermined voltage is at least partially inside the well, biasing the well to the predetermined voltage. Therefore, the minimal spacing requirement between the well and the transistor is eliminated.
In some DRAM embodiments, the channel stop implant mask blocks at least a portion of an area in which the DNW overlaps the precharge transistor drain region. Hence, the channel stop P dopant is prevented from impeding the electrical contact between the DNW and the drain region.
In some embodiments, P and N conductivity types are reversed.
Other features of the invention are described below. The invention is defined by the appended claims.
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Li Li-Chun
Lo Wen-Wei
Pittikoun Saysamone
Wu Chung-Cheng
Wu Huoy-Jong
Ha Nathan W.
MacPherson Kwok & Chen & Heid LLP
Mosel Vitelic Inc.
Park David S.
Pham Long
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