Method of manufacturing field effect transistor

Details Method of manufacturing field effect transistor Method of manufacturing field effect transistor

2002-01-14

2004-10-12

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000

Reexamination Certificate

active

06803288

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor (FET) such as a MOS (Metal Oxide Semiconductor) transistor.
2. Description of the Related Art
In the MOS transistor, with a voltage being applied between a source and a drain being made up of a pair of impurity regions and each being formed at intervals on both sides of a gate electrode formed on a semiconductor substrate, a drain current can be calibrated by controlling a gate voltage to be applied to the gate electrode. When the voltage is applied between the source and the drain, a depletion layer expands in a direction from the drain to the source. Since an excessive expansion of the depletion layer causes a decrease in a threshold voltage of the MOS FET, in order to inhibit the excessive expansion of the depletion layer, an attempt is being made in which, between a pair of first impurity regions each making up the source and drain respectively, a pair of second impurity regions exhibiting a conductive property being reverse to that in the first impurity regions is formed.
Each impurity region making up the pair of the second impurity regions expands from a position of each of the tip portions of the pair of the first impurity regions in a direction that the two impurity regions making up the second impurity regions come closer to one another beneath the gate electrode. Since serial and continued formation of the pair of the second impurity regions causes a decrease in the drain current, to prevent such the decrease in the drain current, each of the pair of the second impurity regions is placed at intervals in a manner so as to avoid such the serial formation. However, in order to obtain a comparatively high effect of inhibiting the expansion of the depletion layer at a low impurity concentration, it is desirous that the depletion layer expands directly beneath the gate electrode as much as possible.
To achieve this, conventionally, when the second impurity regions are formed, after the gate electrode has been formed, an impurity is implanted at predetermined places in the semiconductor substrate using the gate electrode as a selective mask. Moreover, in order to expand the second impurity regions as much as possible beneath the gate electrode, the impurity used to form the second impurity regions is implanted at an angle formed by a line heading from an obliquely upward direction of the gate electrode to the downward direction of the gate electrode and a line being vertical to a surface of the semiconductor substrate in a manner that the angle of depression becomes narrow, that is, in a manner that the angle of implanting the impurity becomes wide in relative to a line being vertical to a surface of the semiconductor substrate.
However, if a plurality of the gate electrodes is formed in parallel, since the second impurity regions are expanded comparatively long, when the angle of implanting the impurity is set to be wide, adjacent gate electrodes shade each other and, if the interval between the gate electrodes is different, each transistor is shaded by the gate electrode, thus causing variations in the impurity concentration of the second impurity regions and in electrical characteristics of each transistor.
Therefore, in the conventional method of manufacturing the FET, it is not easy to produce the FET in which the expansion of the depletion layer between the source and drain has been effectively inhibited by implantation of the ion at a comparatively low impurity concentration.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a method of manufacturing an FET which is capable of effectively inhibiting an expansion of a depletion layer between a source and a drain in the FET without causing variations in electrical characteristics.
It is another object of the present invention to provide the method of manufacturing the FET which is capable of effectively inhibiting the depletion layer at a comparatively low impurity concentration.
According to a first aspect of the present invention, there is provided a method of manufacturing an FET having a gate electrode formed on a semiconductor substrate, with a main surface, the method including:
forming a conductive layer on the main surface via a dielectric film;
forming a gate electrode by etching the conductive layer using a mask formed thereon;
forming a source region and a drain region in the main surface; and
forming pocket regions in the semiconductor substrate by implanting ion using the mask.
According to a second aspect of the present invention, there is provided a method of manufacturing an FET having
a method of manufacturing a field effect transistor having a semiconductor substrate with a main surface, comprising;
forming a conductive layer on the main surface via a dielectric film;
forming a mask on the conductive layer;
forming pocket regions in the semiconductor substrate by implanting ion using the mask;
forming a gate electrode by etching the conductive layer using the mask;
forming a source region and a drain region in the main surface using the gate electrode as a mask; and
wherein the pocket regions underlying the source and drain regions.
In the foregoing, a preferable mode is one wherein the mask has a desired width to define a gate length and wherein an ion is implanted at an angle formed by a line heading from an obliquely upward direction of the mask to a downward portion of the mask and then to an inside of the semiconductor substrate and a line being vertical to a surface of the semiconductor substrate.
Also, a preferable mode is one wherein the mask has a width being less than a desired width defining a gate length and wherein the ion is implanted at a right angle formed by a line heading from an upward direction of the mask to the inside of the semiconductor substrate and a line being vertical to the surface of the semiconductor substrate.
Also, a preferable mode is one wherein side walls are formed on the mask, after the ion implantation, to substantially provide the desired width to the gate electrode and, by using the mask containing the side walls as a resist mask, unwanted portion is removed from the conductive layer and the gate electrode defining a predetermined gate length is formed.
Furthermore, a preferable mode is one wherein, after the ion implantation using the mask, by performing etching processing using the etching mask as a resist mask, the gate electrode whose width is increased along the downward direction to secure the predetermined gate length.
With the above configurations, prior to the formation of the gate electrode, the impurity used to form the pocket regions is implanted by using the etching mask used to form the gate electrode as the selective mask. The selective mask prevents the pair of pocket regions from being formed in a serial and continued manner. Moreover, since the conductive layer formed under the selective mask is in a state before being formed as the gate electrode, it exists in a serial and continued state irrespective of the state of intervals between the gate electrodes, the concentration of the ion to be implanted to form the pocket regions is not affected partially as in the gate electrode manufactured by the conventional method but influenced equally as a whole.
Furthermore, the selective mask can be a shading object in the oblique impurity implantation process, however, the selective mask is so disposed that a depth from a surface of the gate electrode to a predetermined point where the ion is implanted in the semiconductor substrate is larger by the thickness of the conductive layer compared with the depth in a structure of the FET manufactured by the conventional method. Therefore, even if the ion implantation is performed at the same angle as in the conventional method, it is possible to have the pocket region formed by the ion implantation beneath the gate electrode expand longer by the thickness of the conductive layer, compared with the FET manufactured by the

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