Silicon carbide gate transistor and fabrication process

Details Silicon carbide gate transistor and fabrication process Silicon carbide gate transistor and fabrication process

1999-03-01

2004-12-28

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S105000, C438S931000

Reexamination Certificate

active

06835638

ABSTRACT:

FIELD OF THE INVENTION
The preset invention relates generally to integrated circuits, and particularly to a silicon carbide gate field-effect transistor and complementary metal-oxide-semiconductor (CMOS) compatible method of fabrication.
BACKGROUND OF THE INVENTION
Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. As is well known in the art, such a process allows a high degree of integration such that a high circuit density can be obtained with relatively few well-established masking and processing steps. A standard CMOS process is typically used to fabricate FETs that each have a gate electrode that is composed of n-type conductively doped polycrystalline silicon (polysilicon) material.
The intrinsic properties of the polysilicon gate material affect operating characteristics of the FET that is fabricated using a standard CMOS process. Silicon (monocrystalline and polycrystalline) has intrinsic properties that include a relatively small energy band gap (E
g
), e.g. approximately 1.2 Volts, and a corresponding electron affinity (X) that is relatively large, eg. X≈4.2 eV. For example, for p-channel FEKs fabricated by a typical CMOS process, these and other material properties result in a large turn-on threshold voltage (V
T
) magnitude. As a result, the V
T
magnitude must be downwardly adjusted by doping the channel region that underlies the gate electrode of the FET. Doping to adjust the V
T
magnitude typically includes the ion-implantation of acceptor dopants, such as boron, through the polysilicon gate material and an underlying gate insulator into the channel region of the underlying silicon substrate. A typical V
T
magnitude of approximately 0.7 Volts results from the ion-implantation adjustment step.
One drawback of polysilicon gate FETs is that the V
T
magnitude adjustment by ion-implantation is particularly difficult to carry out in semiconductor-on-insulator (SOI) and other thin film transistor technology. In SOI technology, the FET channel region is formed in a semiconductor layer that is formed upon an insulating region of the substrate. The semiconductor layer may be only 1000 Å thick, making it difficult to obtain a sufficiently sharply defined dopant distribution through ion-implantation.
Another drawback of polysilicon gate FETs is that their intrinsic characteristics are likely to change during subsequent high temperature process steps. For example, the polysilicon gate is typically doped with boron impurities that have a high diffusivity in polysilicon. Because of this high diffusion rate, the boron impurities that are introduced into the polysilicon gate electrode of the FET diffuse through the underlying gate oxide during subsequent high temperature processing steps. As a result, the V
T
magnitude the FETs may change during these subsequent high temperature processing steps.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a transistor having an even lower V
T
magnitude, in order to operate at lower power supply voltages. There is an additional need in the art to obtain such lower V
T
magnitudes without using ion-implantation, particularly for thin film transistor devices in a SOI process. There is a further need in the art to obtain V
T
magnitudes that remain stable in spite of subsequent thermal processing steps.
Halvis et al. (U.S. Pat. No. 5,369,040) discloses a charge-coupled device (CCD) photodetector which has transparent gate MOS imaging transistors fabricated from polysilicon with the addition of up to 50% carbon, and preferably about 10% carbon, which males the gate material more transparent to the visible portion of the energy spectrum. However, the Halvis et al. patent is directed to improving gate transmissivity to allow a greater portion of incident light in the visible spectrum to penetrate the gate. Halvis et al. did not recognize the need to improve the gate characteristics of FETs by lowering V
T
magnitudes or stabilizing V
T
magnitudes over subsequent thermal processing steps. Halvis et al. does not disclose or suggest the use of carbon in a field-effect transistor gate in the absence of incident light. Thus, the above described needs are unresolved in the art of fabrication of FETs using CMOS processes.
REFERENCES
Y. Yamaguchi et al., “Properties of Heteropitaxial 3C-SiC Films Grown by LPCVD”, 8th International Conference on Solid-State Sensors and Actuators and Eurosensors IX, Digest of Technical Papers, page 3. vol. (934+1030+85), pages 190-3, Vol. 2, 1995; M. Andrieux, et al., “Interface and Adhesion of PECVD SiC Based Films on Metals”, Le Vide Science, Technique et Applications. (France), No. 279, pages 212-214, 1996; F. Lanois, “Angle Etch Control for Silicon Power Devices”, Applied Physics Letters, Vol 69, No. 2, pages 236-238, July 1996; N. J. Dartnell, et al., “Reactive Ion Etching of Silicon Carbide” Vacuum, Vol. 46, No. 4, pages 349-355, 1955.
SUMMARY OF THE INVENTION
One aspect of the present invention provides a field-effect transistor (FET) having an electrically interconnected gate formed of polycrystalline or microcrystalline silicon carbide (SiC) material. The SiC gate material has a lower electron affinity and a higher work function than a polysilicon gate material. The characteristics of the SiC gate FET include a lower threshold voltage (V
T
) magnitude and a lower tunneling barrier voltage as compared to polysilicon gate FETs.
Another aspect of the invention provides a method for fabricating a transistor including an electrically interconnected SiC gate. Source and drain regions are fabricated in a silicon substrate separated from each other and defining a channel region therebetween. An insulating region is fabricated over the channel region. A SiC gate is fabricated over the insulating region. In one embodiment, SiC gate fabrication includes depositing an SiC layer on the insulating region using low pressure chemical vapor deposition (LPCVD) and etching the SiC material to a desired pattern using a reactive ion etch (RIE) process.
The invention provides numerous advantages. For example, the SiC gate FET provides lower V
T
magnitudes, allowing integrated circuit operation at lower power supply voltages. The lower power supply voltage, in turn, provides advantages including lower power consumption and ease in downward scaling of transistor dimensions without unacceptably increasing electric fields. The lower V
T
magnitudes also enable higher switching and improved performance. The SiC gate FET also provides lower V
T
magnitudes without adjustment by ion-implantation. This is particularly useful for semiconductor-on-insulator (SOI) and other thin film transistor devices in which an adequately sharply defined dopant distribution is difficult to obtain by ion-implantation V
T
adjustment. The SiC gate FET also provides V
T
magnitudes that are stable in spite of subsequent thermal processing steps. The SiC gate FET further provides more optical V
T
magnitudes for n-channel FETs (e.g., enhancement rather than depletion mode).


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