Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-08-22
2004-08-31
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S132000, C438S601000, C257S209000
Reexamination Certificate
active
06784045
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fuses and interconnects formed on semiconductor wafers and the methods for forming them. More particularly, the present invention relates to methods for forming channels on semiconductor wafers to form fuses and interconnects.
2. Description of the Related Art
Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased packing density, therefore increased net die per wafer (numbers of usable chips produced from a standard semiconductor wafer). However, with smaller devices a limiting factor in achieving smaller features and nodes is the wavelength of the light used in the photolithographic process to produce the features.
Photolithography is one of the most important steps of the semiconductor manufacturing process. During the photolithographic process a semiconductor wafer is coated with a light sensitive material called a photoresist or resist and is exposed with an actinic light source. The exposure light passes through a photomask and is imaged via projection optics onto the resist coated wafer forming a reduced image of the photomask in the photoresist. For positive chemically amplified resists, the actinic light source typically causes the production of photoacids that diffuse during post exposure bake and allow the resist to be rinsed away by an aqueous developer in only the regions receiving at least a threshold exposure dose. The last step in the photolithographic process involves etching the resist-coated wafers to attack the semiconductor material not covered with photoresist.
Unfortunately, in order to increase the density on the wafer, i.e., to generate features on the wafer that are smaller than available using the current generation of the photolithography equipment, it is typically necessary to undertake major processing equipment expenditures.
As semiconductor devices, such as integrated circuit chips, continue to decrease in size and increase in complexity, the likelihood of a defective chip resulting from a failed element or a defective conductor increases. One way to reduce the number of chips which must be discarded due to fabrication defects is to manufacture fuses into semiconductor devices. Fuses may be opened to isolate defective areas and allow the rest of the circuit on a chip to be used. Fuses may also be used to trim a circuit, enable a particular mode, or enable or disable different segments of a circuit, such as for example in configuring customer circuits on programmable logic devices (PLD's).
Often it is desirable to create fuses or other components having dimensions smaller than the other patterned features in a particular layer on a wafer. Thus, even though it may be desirable to form a fuse having a much smaller width than the interconnect lines in the same layer, conventional patterning and fill techniques limit the variance in widths that can be efficiently filled in the same step.
For example, scaling of devices may result in a device structure having one or more thick metal redistribution layers to efficiently distribute power across the chip while minimizing the voltage drop along the power lines. Generally it is advisable to have thick redistribution metal layers to avoid a voltage drop from the periphery to the center of the chip. However, these thick redistribution layers may be unsuitable for use in the formation of metal fuses. Redistribution layers, for example, may be about 1.0 to 3.0 microns in thickness in 0.13 micron device technology, thus making it difficult to blow the fuse without exceeding the thermal capacity of the device. Copper's high thermal conductance characteristic requires greater heat to blow the fuse than a same thickness fuse made from other metals such as aluminum. It would be desirable to form thin fuses in the same level as the redistribution layers.
Unfortunately, there is no conventional process that resolves these patterning issues in a satisfactory manner. Accordingly, what is needed is an improved process for forming very small conductive channels that can be integrated in the same layer with conventional patterned features having larger dimensions, thus increasing the density of the chips and providing greater flexibility.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides methods for forming interconnects and fuses on a semiconductor wafer in small enclosed conduits, i.e., microchannels. The processing sequence involves forming on a wafer a structure having sufficient topography such as a gap between two structures to create an enclosed conduit when a dielectric is deposited to fill the gap. Via holes are then formed to intersect the enclosed hollow conduit. The conduit is then filled followed by planarization to yield a conductive line located in the gap or trench defined by the patterned structures. By processing the semiconductor wafer in this manner, conductive lines of small cross-section may be formed, as may be suitable for resistors, fuses and other applications.
According to one embodiment, a method of forming a conductive line on a semiconductor substrate is provided. A trench is first formed on the semiconductor wafer. A dielectric material is deposited in the trench to form a hollow enclosed conduit. One or more via holes are formed in the dielectric and configured to intersect the hollow enclosed conduit. The hollow conduit is then filled using at least one via hole. Preferably, at least one of the via holes are filled and used to make electrical connection to the conduit.
According to another embodiment, the conductive line is formed by a metal selected from Ti, TiN, W, Al, Cu, and Mb. According to yet another embodiment, the conduit is configured to form one of a fusible link, resistor, capacitor, interconnect, and inductor.
According to yet another embodiment, the conductive line is formed from a conduit that is hollow. The hollow conductive line is then filled with a dielectric material in an annular shape. The space defined by the annular shape is then filled with a second conductive material to form a second conductive line.
These and other features and advantages of the present invention are described below with reference to the drawings.
REFERENCES:
patent: 6174802 (2001-01-01), Huang et al.
patent: 6211698 (2001-04-01), Suh
Kalpathy-Cramer Jayashree
Price David T.
Beyer Weaver & Thomas
Lee Calvin
Smith Matthew
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