Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-28
2004-08-10
Yevsikov, Victor V (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S210000, C438S275000, C438S224000, C438S229000, C438S231000, C438S286000, C438S305000, C438S346000, C438S301000, C257S407000, C257S408000, C257S757000
Reexamination Certificate
active
06773978
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor device processing and more particularly to methods for fabricating metal transistor gates in the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor products, individual transistors and other electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form circuits. Electrical connections are typically made to transistor gate and source/drain terminals by forming silicide contacts thereover. Interlayer dielectric (ILD) material is then formed over the wafer, through which vias are etched and filled with conductive material (e.g., tungsten, copper, or the like) to provide electrical connection to the gate and source/drain silicide contacts. Interconnection of the various devices is then accomplished by forming a multi-level interconnect network in layers formed over the electrical devices, by which the device active elements are connected to other devices to create the desired circuits in the finished integrated circuit
Referring to
FIGS. 1A-1F
, the formation of silicide contacts in many transistor fabrication processes is done simultaneously for a polysilicon gate
4
and the source/drain regions
6
a
and
6
b
of a MOS type transistor
2
fabricated in a substrate
8
, using a self-aligned silicide process (salicide). The source/drain regions
6
a
and
6
b
are laterally spaced in the substrate
8
to define a channel region
10
in the substrate
8
, over which a thin gate oxide
12
is formed. The polysilicon gate structure
4
is formed over the gate oxide
12
and sidewall spacers
14
are formed on the lateral sides of the gate
4
and gate oxide
12
, wherein the source/drain regions
6
a
and
6
b
are provided with dopants in one or more process steps to provide the structure of FIG.
1
A.
A nickel (Ni) layer
20
is then formed over the device
2
in
FIG. 1B
by a deposition process
22
. In
FIG. 1C
, a first thermal process
24
is employed to react the upper portions of the gate polysilicon
4
and the source drain substrate regions
6
a
,
6
b
with the nickel
20
. The first thermal process is typically performed at a relatively low temperature, such as below 500 degrees C. This results in formation of first phase nickel silicide (Ni
2
Si+NiSi) contacts
26
a
and
26
b
over the source/drains
6
a
and
6
b
, respectively, as well as a first phase nickel silicide Ni
2
Si contact
26
c
over the remaining (e.g. non-consumed) polysilicon gate
4
.
An etch process
30
is performed in
FIG. 1D
to remove the remaining unreacted nickel
20
and a second thermal process
32
is employed in
FIG. 1E
to transform the first phase nickel silicide Ni
2
Si+NiSi contacts
26
a
-
26
c
into second phase nickel silicide NiSi contacts
26
a
′-
26
c
′, where the second phase silicide NiSi contacts
26
a
′-
26
c
′ are of lower resistance than the first phase silicide Ni
2
Si
26
a
-
26
c
. Interconnect layers are then formed over the device
2
, as illustrated in
FIG. 1F
, including ILD dielectric material
34
and conductive contacts
36
a
-
36
c
formed in vias to make connection with the silicide contacts
26
a
′-
26
c
′, respectively. The resulting structure of
FIGS. 1E and 1D
provides a gate consisting of the phase two silicide
26
c
′, the polysilicon
4
, and the gate oxide
12
overlying the channel region
10
of the substrate
8
.
However, as device sizes continue to be scaled, and as device performance continues to be improved, it is desirable to reduce the work function of transistor gates. The work function represents the energy required to move an electron in a solid atom from the Fermi level to the vacuum level outside of the atom, and is used to compare the energy states of various elements and to predict electrical properties of the contact between them. The work function of the gate of the transistor
2
is based on silicon-oxide-silicon interfaces, corresponding to the interfaces between the polysilicon
4
, the gate oxide
12
, and the silicon channel
10
. Thus, there is a need for improved techniques for processing transistor gates by which reduced gate work functions can be achieved.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention involves methods for silicide metal gate formation in which a single thermal process is used to react gate polysilicon with and overlying metal layer to form a conductive second phase metal silicide gate extending from the bottom surface to the top surface, which consumes substantially all the polysilicon. The process is performed as a separate silicide for the transistor gate only, wherein the source/drain regions may be covered during the single-step thermal gate silicide process, and a separate source/drain region silicide: process is employed to provide silicide source/drain contacts. In one implementation of the invention, a single rapid thermal anneal (RTA is used at about 500 degrees C. or more to react the metal layer nickel or cobalt with polysilicon to form phase two silicide material (e.g., NiSi or CoSi
2
) in a single thermal step, in which little or no interface roughness is found at the silicide/gate oxide interface. Thus, the invention facilitates adjustment and control of the gate work function by reducing the non-uniformity thereof. This, in turn provides the advantages of silicide metal gates without the transistor gate work function non-unifornities found in prior devices.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 4912061 (1990-03-01), Nasr
patent: 4997779 (1991-03-01), Kohno
patent: 5937315 (1999-08-01), Xiang et al.
patent: 6096595 (2000-08-01), Huang
patent: 6100145 (2000-08-01), Kepler et al.
patent: 6140167 (2000-10-01), Gardner et al.
patent: 6265749 (2001-07-01), Gardner et al.
patent: 6268255 (2001-07-01), Besser et al.
patent: 6274511 (2001-08-01), Wieczorek et al.
patent: 6326251 (2001-12-01), Gardner et al.
patent: 6329277 (2001-12-01), Liu et al.
patent: 6342414 (2002-01-01), Xiang et al.
patent: 6368950 (2002-04-01), Xiang et al.
patent: 6372673 (2002-04-01), Besser et al.
patent: 6376343 (2002-04-01), Buynoski et al.
patent: 6380057 (2002-04-01), Buynoski et al.
patent: 6387767 (2002-05-01), Besser et al.
patent: 6391750 (2002-05-01), Chen et al.
patent: 6410967 (2002-06-01), Hause et al.
patent: 6534837 (2003-03-01), Bai et al.
Besser Paul Raymond
Pan James
Paton Eric
Advanced Micro Devices , Inc.
Yevsikov Victor V
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