Collar dielectric process for reducing a top width of a deep...

Details Collar dielectric process for reducing a top width of a deep... Collar dielectric process for reducing a top width of a deep...

2003-08-18

2004-11-23

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S249000

Reexamination Certificate

active

06821844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a deep trench capacitor, and more particularly to a collar dielectric process for a deep trench capacitor in order to reduce the top width of the deep trench.
2. Description of the Related Art
A DRAM cell comprises a transistor coupled to a capacitor. Currently in the semiconductor industry, DRAM cell includes a deep trench capacitor and a planar transistor. The deep trench capacitor is a three dimensional structure formed in a silicon substrate, and has the advantages of smaller memory area, lower power consumption and higher operating speed.
FIG. 1A
is a plane view illustrating the arrangement of deep trenches, word lines and bit lines in a conventional DRAM cell. For a folded bit line structure, each active area comprises two word lines WL
1
and WL
2
and one bit line BL, in which the character “DT” indicates the deep trench, and the character “PC” indicates a bit line contact.
FIG. 1B
is a cross-section illustrating a conventional deep trench capacitor of a DRAM cell. A deep trench DT is formed in a silicon substrate
10
, and a deep trench capacitor
12
is formed in the lower portion of the deep trench DT. The deep trench capacitor
12
is composed of a buried plate, a node dielectric and a storage node. The conventional method of forming the deep trench capacitor
12
employs the following steps. First, a reactive ion etching (RIE) method is used to form the deep trench DT in the p-type silicon substrate
10
. A high-temperature and short-term annealing process using a heavily-doped oxide material (such as ASG) is performed. N
+
ions are diffused into the silicon substrate
10
at the lower portion of the deep trench DT, thus forming an n
+
-type diffusion region
14
to serve as the buried plate of the deep trench capacitor
12
. Next, a silicon nitride layer
16
is formed on the sidewall and bottom of the lower portion of the deep trench DT to serve as the node dielectric of the deep trench capacitor
12
. Next, a first n
+
-doped polysilicon layer
18
is deposited to fill the deep trench DT after which it is recessed to reach a predetermined depth, thus serving as the storage node of the deep trench capacitor
12
.
After completing the deep trench capacitor
12
, a collar dielectric layer
20
is formed on the sidewall of the upper portion of the deep trench DT, after which a second n
+
-doped polysilicon layer
22
is deposited to fill the deep trench DT. Then, a third polysilicon layer
24
is formed over the second polysilicon layer
22
. Subsequently, processes for STI (shallow trench isolation) structure
26
, the word lines WL
1
and WL
2
, a source/drain diffusion region
28
, and the bit line contact BC and the bit line BL are performed thereon. The STI structure
26
is used to isolate two adjacent DRAM cells.
In addition, a buried strap outdiffusion region
30
is formed in the silicon substrate
10
at the top portion of the deep trench DT for connecting the deep trench capacitor
12
to a planar transistor. Thus, the buried strap outdiffusion region
30
is also called a node junction. Typically, using thermal annealing, the n
+
ions of the second polysilicon layer
22
can diffuse into the silicon substrate
10
through the third polysilicon layer
24
to form the buried strap outdiffusion region
30
. Thus, the third polysilicon layer
24
is also called a buried strap
24
.
The collar dielectric layer
20
is required to isolate the buried strap outdiffusion region
30
from the buried plate
14
because current leakage of the buried strap outdiffusion region
30
to the buried plate
14
may degrade the retention time of the DRAM cell. The conventional method for the collar dielectric layer
20
increases the top width of the deep trench DT, which limits the WL-DT (word line to deep trench) overlay tolerance and the distribution of the buried strap outdiffusion region
30
. Particularly, the increased top width of the deep trench DT reduces an overlay margin area L between the source/drain diffusion region
28
and the buried strap outdiffusion region
30
, resulting in serious junction leakage and worse sub-Vt performance.
FIGS. 2A
to
2
E are cross-sections illustrating a conventional method for the collar dielectric layer
20
shown in FIG.
1
B. In
FIG. 2A
, the p-type semiconductor silicon substrate
10
is provided with the deep trench capacitor
12
at the lower portion of the deep trench DT. The capacitor process includes steps of forming a silicon nitride pad layer
32
, the deep trench DT, the n
+
-type diffusion region
14
, the silicon nitride layer
16
and the n
+
-doped first polysilicon layer
18
. Then, in
FIG. 2B
, the silicon nitride layer
16
is removed from the upper portion of the deep trench DT, after which the first polysilicon layer
18
is recessed. Next, an oxidation process is performed to grow a first silicon oxide layer
34
on the exposed surface of the silicon substrate
10
. The first silicon oxide layer
34
covers the sidewall of the upper portion of the deep trench DT to ensure the isolation result between the n
+
-type diffusion region
14
and the buried strap outdiffusion region
30
which will be formed in subsequent processes. Next, in
FIG. 2C
, a chemical vapor deposition (CVD) method is employed to conformally deposit a second silicon oxide layer
36
, after which an anisotropic dry etching method is employed to remove the second silicon oxide layer
36
from the top of the first polysilicon layer
18
.
Next, in
FIG. 2D
, the second n
+
-doped polysilicon layer
22
is deposited to fill the deep trench DT, after which it is recessed to reach a predetermined depth. Finally, in
FIG. 2E
, a wet etching method is employed to remove portions of the second silicon oxide layer
36
and the first silicon oxide layer
34
until the top of the second polysilicon layer
22
protrudes from the second silicon oxide layer
36
and the first silicon oxide layer
34
. Thus, the remaining portion of the second silicon oxide layer
36
and the first silicon oxide layer
34
serves as the collar dielectric layer
20
.
During the oxidation process for growing the first silicon oxide layer
34
, a part of the silicon substrate
10
is converted into SiO
2
, thus the top width of the deep trench DT is increased through the subsequent wet etching process. This reduces an overlay margin area L between the source/drain diffusion regions
28
and the buried strap outdiffusion region
30
, resulting in serious junction leakage and worse sub-Vt. The oxidation process for the first silicon oxide layer
34
is the main factor in increasing the top width of the deep trench DT, but is important nonetheless, and cannot be skipped as more serious junction leakage will occur if the first silicon oxide layer
34
is thinned or omitted. Accordingly, based on the prerequisite oxidation for the first silicon oxide layer
34
, a novel collar dielectric process of reducing the top width of the deep trench DT is called for.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a collar dielectric process with an ion implantation process for selectively growing a silicon oxide layer on the sidewall of a deep trench outside a buried strap outdiffusion region.
According to the object of the invention, a collar dielectric process for reducing a top width of a deep trench has the following steps. A semiconductor silicon substrate has a deep trench and a deep trench capacitor. The deep trench capacitor has a node dielectric formed on the sidewall and bottom of the deep trench, and a storage node formed in the deep trench and reaching a predetermined depth. An ion implantation process is performed to form an ion implantation area on the substrate at the top of the deep trench. The node dielectric is then removed until the top of the node dielectric is leveled off with the top of the storage node, thus exposing the sidewall of the deep trench outside the deep trench capacitor. Next, an oxida

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