Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2003-01-22
2004-02-24
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S783000, C257S698000, C438S108000
Reexamination Certificate
active
06696764
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flip chip type semiconductor device having a semiconductor chip mounted on its multilayer wiring board and a method of manufacturing the same. In particular, the present invention relates to a flip chip type semiconductor device and a method of manufacturing the same, that is low in manufacturing cost and capable of reducing the wiring pattern pitch of the multilayer wiring board to 10 &mgr;m or less.
2. Description of the Related Art
FIGS. 1A and 1B
are side views showing a conventional flip chip type semiconductor device
101
. The flip chip type semiconductor device
101
shown in
FIG. 1A
has a semiconductor chip
102
, on the peripheral region or active region of which external terminals (not shown) are formed in an area array. Bumps
103
of metal material such as solder, Au, or an Sn—Ag alloy are formed as protruded from the external terminals.
As shown in
FIG. 1B
, the flip chip type semiconductor device
101
is mounted on a multilayer wiring mounting board
104
. The multilayer wiring mounting board
104
has electrode pads (not shown) that are formed in the same pattern as the arrangement pattern of the bumps on the flip chip type semiconductor device
101
. The flip chip type semiconductor device
101
is mounted on the multilayer wiring mounting board
104
by end users with the bumps
103
in alignment with the electrode pads. When the bumps are made of solder, the flip chip type semiconductor device
101
is typically mounted on the multilayer wiring mounting board
104
by an IR reflow process using flux.
The conventional flip chip type semiconductor device
101
, however, has the problem that after the mounting on the multilayer wiring mounting board
104
, it deteriorates in mounting reliability, or temperature cycle characteristics in particular, due to a mismatch in the coefficient of linear expansion between the multilayer wiring mounting board
104
and the flip chip type semiconductor device
101
. To solve this problem, the following measures have been taken heretofore.
First, it has been attempted to bring the coefficient of linear expansion of the multilayer wiring mounting board
104
close to that of silicon. For example, as disclosed in Japanese Patent Laid-Open Publication No. 2000-323620, ceramic type materials such as AlN, mullite, and glass ceramic, which are expensive, are used to minimize the mismatch in the coefficient of linear expansion for the sake of improved mounting reliability. This attempt is effective in terms of improvement in mounting reliability, whereas the use of the expensive ceramic type materials for the multilayer wiring board usually limits the applications to high-end super computers, large scale computers, and the like.
On the contrary, as disclosed in Japanese Patent Laid-Open Publication No. 2001-203237, for example, there has recently been proposed a technology capable of improving the mounting reliability in which a flip chip type semiconductor device is packaged with an underfill resin interposed between a multilayer wiring board made of inexpensive organic material having a high coefficient of linear expansion and a semiconductor chip. When an underfill resin is thus arranged between the semiconductor chip and the multilayer wiring board made of organic material, shearing stress acting on the bump connecting portions lying between the semiconductor chip and the multilayer wiring board made of organic material can be dispersed for improved mounting reliability. The interposition of the underfill resin between the semiconductor chip and the organic-material multilayer wiring board thus allows the use of the multilayer wiring board that is made of inexpensive organic material.
This conventional art, however, has the problem that the interface between the underfill resin and the semiconductorchip and the interface between the underfill resin and the organic-material multilayer wiring board might suffer delamination and the product might be judged to be defective in a moisture absorption reflow test if the underfill resin contains voids or if the interfaces are poor in adhesive properties. It is therefore impossible for this conventional art to promote a cost reduction of the flip chip type semiconductor device with reliability.
In consideration of the minimum pitch in a bump arrangement pattern and the pin counts, a multilayer wiring board so-called build-up board is typically used as the organic-material multilayer wiring board of the flip chip type semiconductor device. Hereinafter, the method of manufacturing a build-up board will be described with reference to
FIGS. 2A
through
3
C.
FIGS. 2A through 2C
are sectional views of a conventional build-up board, showing the method of manufacturing the same in the order of steps.
FIGS. 3A through 3C
are sectional views showing the steps subsequent to that of FIG.
2
C.
In
FIG. 2A
, a Cu foil layer
111
having a predetermined thickness such as 10 to 40 &mgr;m is initially pasted on both sides of a core substrate
110
of insulative glass epoxy material, followed by patterning. A hole is drilled in the core substrate
110
before through-hole plating is applied to the interior of the hole, thereby forming a through hole part
112
. As a result, the Cu foil layers
111
on both sides of the core substrate
110
are electrically connected with each other. Here, in view of the process stability in the subsequent steps and the quality stability of the substrate, the through hole part
112
is typically filled with an insulative through hole filling resin
113
.
As shown in
FIG. 2B
, an insulative resin
114
is applied to the Cu wiring patterns lying on both sides of the core substrate
110
. Insulative resin openings
115
are formed in predetermined positions by photoresist-based chemical etching or a laser machining technique.
As shown in
FIG. 2C
, metal thin film layers
116
are formed by sputtering metal such as Ti and Cu or through Cu electroless plating, in order that electric connection shall be secured between feed layers intended for Cu electroplating and Cu wiring pattern parts on the core substrate.
As shown in
FIG. 3A
, photoresists
117
or dry films having a thickness of 20 to 40 &mgr;m are arranged on the metal thin film layers
116
and then subjected to exposure and development for the sake of wiring pattern formation through Cu electroplating.
As shown in
FIG. 3B
, wiring pattern parts
118
are formed by Cu electroplating with the metal thin film layers
116
as the feed layers.
As shown in
FIG. 3C
, the photoresists
117
or dry films are removed. Using the wiring pattern parts
118
as a mask, the metal thin film layers
116
are then removed by wet etching, so that the wiring pattern parts
118
are electrically independent of each other.
Subsequently, the steps of
FIGS. 2B
to
3
C can be repeated to form a multilayer wiring board having a six- or eight-layer metal structure if needed.
Considering a relaxation of stress resulting from a mismatch in the coefficient of thermal expansion with the core substrate and reliabilities of the multilayer wiring board such as that of the connection via portions, however, the foregoing method of manufacturing a build-up board requires that the photoresists
117
or dry films have a thickness of around 20 to 40 &mgr;m to secure the thickness of the build-up layer wiring pattern portions. Thus, in terms of pattern formability at the exposure and development steps, a minimum pitch of 30 &mgr;m or so can only be achieved at best. This results in a wiring pattern pitch no smaller than 30 &mgr;m or so, which precludes higher densities of the multilayer wiring board and smaller outside dimensions of the board. In typical manufacturing processes, build-up boards are fabricated together on a large panel of approximately 500 mm×600 mm, and then cut into individual pieces of multilayer wiring boards in the final step. The number of pieces producible per panel can thus be increased if each multilayer wiring board is s
Clark Sheila V.
NEC Electronics Corporation
Young & Thompson
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