Semiconductor device with an improved gate electrode pattern...

Details Semiconductor device with an improved gate electrode pattern... Semiconductor device with an improved gate electrode pattern...

2003-07-07

2004-12-21

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S283000, C438S381000

Reexamination Certificate

active

06833301

ABSTRACT:

BACKGROUND OF THE INVENTION
This application is a Divisional of U.S. application Ser. No. 09/418,035 filed on Oct. 14, 1999, now U.S. Pat. No. 6,653,695, hereby incorporated by reference as to its entirety. This application is based upon and claims the benefit of priority from the prior Japanese Patent Application 10-293901, filed Oct. 15, 1998, the entire contents of which are incorporated herein by reference. The present invention relates to a gate structure of a semiconductor device and, particularly, to a cell layout of an SRAM (Static Random Access Memory) having a MOS transistor and to a reticle pattern for producing a semiconductor device.
Products of semiconductor devices such as ICs and LSIs are produced basically through a design step (functional design, logical design, layout design and the like) and a production test step (chip production step, test evaluation step and the like). Process technologies for semiconductor devices have come to be established in a new generation deep submicron technologies. With this progress, the width of wirings used in semiconductor devices has come to be reduced to 0.3 &mgr;m or less. However, such a tendency of a reduction in, for instance, the width of wirings of, e.g., polysilicon wirings, makes it impossible to neglect a microscopic variation in the width of wirings which is caused by a optical proximity effect. The optical proximity effect is a phenomenon that the finishing value of the wiring width of the polysilicon wiring is changed by a space between this wiring and an adjacent polysilicon wiring. In other words, this is a phenomenon that dimensional accuracy is impaired by a optical proximity effect when, along with miniaturization and densifying of a pattern in a semiconductor device, a charge beam exposure apparatus or an optical reduction-projection exposure apparatus is used in the printing and exposing such a pattern.
Highly integrated and high performance semiconductor devices have been developed by virtue of a development and progress in fine processing techniques. In lithographic techniques which play an important role among the fine processing techniques, techniques such as the use of light with shorter wavelengths, a development of photoresist materials having higher resolution and a formation of a more thinned film of photoresist materials on the premise that a highly uniform film is applied owing to an improvement in a control of the thickness of photoresist films greatly contribute to an improvement in the fine techniques. However, the above high resolution techniques cannot allow the same processing accuracy and margin in a lithographic step as in the case of using a line-space pattern as a simple fine pattern.
This problem of fidelity of a pattern greatly affects miniaturization of, for instance, SRAMs forming six MOSFETs in one memory cell.
FIG. 7
is a top plan view showing a cell layout of an SRAM suitable for miniaturization. This SRAM is characterized in that, by connecting a drain of a load transistor (pMOS transistor) of an SRAM cell to a drain of a drive transistor (nMOSFET) by using a local interconnect
23
of tungsten (W) (see FIG.
15
and FIG.
16
), a metal wiring is used only for connection between a gate electrode and local interconnects to produce a simple and highly symmetric pattern in contrast with the case of a memory cell using no local interconnect, thereby achieving a reduction in cell area.
FIG. 9
is a sectional view of the SRAM cell suitable for miniaturization which is shown in FIG.
7
.
FIG. 21
is a top plan view showing a wiring section in a cell layout of the SRAM shown in FIG.
7
.
FIG. 22
is a top plan view showing a wiring section in a cell layout of the SRAM shown in FIG.
8
. It is clear from these figures that the SRAMs using local interconnects serve to reduce a cell area.
FIGS. 10A and 10B
,
FIGS. 11A and 11B
,
FIGS. 12A and 12B
,
FIGS. 13A and 13B
,
FIGS. 14A and 14B
,
FIG. 15
, and
FIG. 16
are sectional views showing a process flow in the production of the SRAM shown in FIG.
7
. An SiO
2
film
32
with a thickness of, for example, 10 nm is formed on a p-type silicon semiconductor substrate
1
by thermal oxidation. A polycrystal silicon film
33
with a thickness of about 200 nm is formed on the SiO
2
film
32
by an LP-CVD method. A silicon oxide film (SiO
2
)
34
with a thickness of about 200 nm is formed on the polycrystal silicon film
33
by an LP-CVD method. Then, an element region is coated with a photoresist pattern
35
by a photographic etching method (FIG.
10
A).
The silicon oxide film
34
is etched by anisotropic dry etching having a high selective ratio to a polycrystal silicon film by using the photoresist pattern as a mask to exfoliate the photoresist pattern
35
. Using the resulting silicon oxide film
34
thus formed as a mask, the polycrystal silicon
33
is then etched by anisotropic dry etching capable of taking a wide selective ratio to an oxide film. Moreover, the thermal oxide film
32
is etched and thereafter the silicon semiconductor substrate
31
is etched to a depth of 0.5 &mgr;m by anisotropic dry etching capable of taking a wide selective ratio to an oxide film to form a groove section
45
of an STI (Shallow Trench Isolation) (FIG.
10
B).
After that, an 1.5-&mgr;m-thick silicon oxide film (SiO
2
)
37
is deposited by an LP-CVD method (FIG.
11
A). Then, the silicon oxide film
37
is planarized by chemical mechanical polishing capable of taking a high selective ratio to polycrystal silicon. After being planarized, the silicon oxide film
37
is etched either using NH
4
F or by dry etching until the polycrystal silicon film
33
is just exposed (FIG.
11
B). Thereafter the polycrystal silicon film
33
is etched by isotropic dry etching capable of taking a wide selective ratio to a silicon oxide film to form a buried oxide film
36
. Heat treatment for reducing the film stress of the silicon oxide film
36
is then carried out at, for example, 1000° C. In succession, the silicon oxide film formed on the silicon semiconductor substrate
12
is etched using NH
4
F, followed by, for example, thermal oxidation performed at 800° C. to form a silicon oxide film (SiO
2
)
38
. After that, a photoresist pattern is formed by photographic etching and P-type and N-type impurities are introduced into the semiconductor substrate
12
by ion-implantation. Thereafter, impurity atoms are activated by heat treatment at 1000° C. to form a P-well
39
and an N-well
40
and to adjust the threshold value of a MOS transistor formed there (FIG.
12
A).
Next, the thermal oxide film
38
formed on the silicon semiconductor substrate
12
is removed and a gate insulation film (SiO
2
)
41
with a thickness of about 6 nm is formed by a thermal oxidation method at 750° C. Thereafter, a polycrystal silicon film with a thickness of 300 nm is deposited by an LP-CVD method. A photoresist pattern for a gate electrode is further formed by a photographic etching method and a patterning of the polycrystal silicon film is carried out by anisotropic dry etching capable of taking a sufficient selective ratio to silicon oxide to form a gate electrode
42
(FIG.
12
B). Then, a silicon oxide film (SiO
2
) with a thickness of, for example, 5 nm is formed on the silicon semiconductor substrate
12
by a thermal oxidation method at 800° C. In succession, using a photoresist pattern formed by photographic etching, for instance As is introduced into the n-MOS transistor region at an acceleration voltage of 35 keV and a dose of 2E14 cm
−2
and, for instance, BF
2
is introduced into the p-MOS transistor region at an acceleration voltage of 15 keV and a dose of 2E14 cm
−2
. Heat treatment is then performed at 1000° C. for 30 seconds in a N
2
atmosphere to form an n
+
impurity diffused region
44
and a p
+
impurity diffused region
45
(Shallow Extension region). A silicon nitride film (SiN) with thickness of about 150 nm is deposited by an LP-CVD method and the substrate is etched by anisotropic etching capable of taking a high selective

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