Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-17
2004-11-02
Guerrero, Maria (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S231000, C438S303000, C438S305000, C438S275000, C438S276000, C438S587000
Reexamination Certificate
active
06812085
ABSTRACT:
This application claims the benefit of Korean Application No. P2000-41369 filed Jul. 19, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same which improve the characteristic of stand-by current of an SRAM cell.
2. Background of the Related Art
A related art semiconductor device and method for fabricating the same will be described with the accompanying drawings.
FIG. 1
is a cross-sectional view showing a related art semiconductor device, and
FIGS. 2A
to
2
D are cross-sectional views showing fabricating process steps of the related art semiconductor device. In the drawings, left sides are cross-sectional views of a transistor formed in a peripheral area of an SRAM while right sides are cross-sectional views of a transistor formed in a cell area of the SRAM.
As shown in
FIG. 1
, a cell area and a peripheral area of the SRAM are defined in a semiconductor substrate
101
. A gate electrode
103
is formed on the semiconductor substrate
101
, and a gate oxide film
102
is interposed between the semiconductor
101
and the gate electrode
103
. In both the cell area and the peripheral area, heavily doped source/drain regions
106
are formed in the semiconductor substrate
101
at predetermined depths with the same distance from the gate electrode
103
. Subsequently, lightly doped source/drain regions
110
are formed in the semiconductor substrate
101
between the gate electrode
103
and the heavily doped source/drain regions
106
at predetermined depths.
The lightly doped source/drain regions
110
of the peripheral area and the cell area are formed with the same length as shown in portions A and B of FIG.
1
.
Afterwards, a cobalt silicide layer
109
is formed on surfaces of the gate electrode
103
and the heavily doped source/drain regions
106
.
Now, a method for fabricating the aforementioned related art semiconductor device will be described with reference to
FIGS. 2A
to
2
D.
The transistor of the cell area and the transistor of the peripheral area are formed at the same time.
As shown in
FIG. 2A
, the cell area and the peripheral area are defined in the semiconductor substrate
101
and the gate oxide film
102
is formed on the entire surface of the semiconductor substrate
101
. Then, a polysilicon layer for gate electrode is deposited on the gate oxide film
102
.
Afterwards, the polysilicon layer and the gate oxide film
102
are selectively removed by photolithography and etching processes to form the gate electrode
103
on the semiconductor substrate
101
of the cell area and the peripheral area.
A titanium nitride(TiN) layer is then deposited along the surfaces of the gate electrode
103
and the semiconductor substrate
101
by chemical vapor deposition (CVD). A silicon oxide (SiO
2
) layer is deposited on the TiN layer.
The silicon oxide layer and the TiN layer are etched back to remain on both sides of the gate oxide film
102
and the gate electrode
103
as well as on the semiconductor substrate
101
adjacent to both sides, so that a nitride film spacer
104
and an insulating spacer
105
are formed thereon.
As shown in
FIG. 2B
, the insulating spacer
105
is removed, and then heavily doped impurity ions are injected into the entire surface of the semiconductor substrate
101
using the nitride film spacer
104
as a mask, so that the heavily doped source/drain regions
106
are formed in the semiconductor substrate
101
at both sides of the gate electrode
103
and the nitride film spacer
104
at predetermined depths.
As shown in
FIG. 2C
, a cobalt layer
107
and a TiN layer
108
are sequentially deposited on the entire surface of the semiconductor substrate
101
including the gate electrode
103
. At this time, instead of Co of the cobalt layer
107
, any one of refractory metals such as W, Ti and Mo may be used.
As shown in
FIG. 2D
, a cobalt silicide layer
109
is formed on the surfaces of the heavily doped source/drain regions
106
and the gate electrode
103
by a rapid thermal annealing (RTA) process. The cobalt silicide layer
109
includes a cobalt silicide which is a material obtained by reacting silicon of the heavily doped source/drain regions
106
and the gate electrode
103
with cobalt of the cobalt layer
107
.
Afterwards, the TiN layer and the cobalt layer
107
which remain without reacting with silicon are removed and then a secondary RTA process is performed for stabilization of the cobalt silicide layer
109
.
The nitride film spacer
104
is then removed. Subsequently, as shown in portions A and B of
FIG. 2D
, the lightly doped source/drain regions
110
having the same length in the peripheral area and the cell area are formed in the semiconductor substrate
101
in which the cobalt silicide layer
109
is not formed, at both sides of the gate electrode
103
by injecting lightly doped impurity ions using the cobalt silicide layer
109
as a mask. Thus, the related art semiconductor device is completed.
However, the related art semiconductor device and method for fabricating the same the following problems.
Since the distance between the gate electrode and the heavily doped source/drain regions formed in the cell area is equal to the distance between the gate electrode and the heavily doped source drain regions formed in the peripheral area, it is difficult to reduce lateral field of the transistor of the cell area. This results in leakage of stand-by current such as gate induced drain leakage (GIDL) when the SRAM cell is not operating.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a semiconductor device and a method for fabricating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor device and a method for fabricating the same which improve characteristic of stand-by current of an SRAM cell.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve at least these objects and other advantages in a whole or in part and in accordance with purposes of the present invention, as embodied and broadly described, a semiconductor device according to the present invention comprises a semiconductor substrate in which a peripheral area and a cell area are defined, a first and second gate insulating layers on the semiconductor substrate of the peripheral area and the cell area, first and second gate electrodes on the first and second gate insulating layers, respectively, first and second heavily doped source/drain regions in the semiconductor-substrate at both sides of the first gate electrode and the second gate electrode, respectively, first and second lightly doped source/drain regions in the semiconductor substrate, adjacent to the first heavily doped source/drain regions and the second heavily doped source/drain regions, respectively, wherein the first and second lightly doped source/drain regions have a different length, and a silicide layer on the first and second gate electrodes and in the first and second heavily doped source/drain regions.
In another aspect, a method for fabricating a semiconductor device according to the present invention comprises the steps of defining a peripheral area and a cell area in a semiconductor substrate to form a first and second gate electrodes in the peripheral area and the cell area, respectively, forming a first insul
Guerrero Maria
Hynix Semiconductor Inc
Jacobson & Holman PLLC
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