Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-30
2004-02-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S275000, C438S592000
Reexamination Certificate
active
06696333
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the structure and fabrication of integrated circuits, and more particularly to integrated circuits having metal oxide semiconductor field effect transistors (MOSFETs) with multi-layer metal gate electrodes.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of tens, and more recently hundreds, of millions of circuit elements, such as transistors, on a single integrated circuit (IC). To achieve such dramatic increases in the density of circuit components has required semiconductor manufacturers to scale down the physical dimensions of the circuit elements, as well as the interconnection structures used to connect the circuit elements into functional circuitry.
One consequence of scaling down the physical dimensions of circuit elements has been a dramatic increase in the complexity of transistor engineering for the process engineers and scientists that develop advanced microelectronic manufacturing processes. In the past it was common to consider gate oxide thickness, polysilicon line width, source/drain junction depth and lateral diffusion therefrom, and some threshold adjusting ion implant as the entered the deep submicron region, the transistor structure became more complex with the inclusion of elements such as graded well doping, epitaxial wafers, halo implants, tip implants, lightly doped drain structures, multiple implants for source/drain formation, silicidation of gates and source/drains, and multiple sidewall spacers, among others. Because of the complex nature of deep submicron transistors, workers in this field tend to characterize, or specify, transistors not so much by physical dimension (e.g., gate length) but rather by electrical characteristics such as drive current (I
on
) versus leakage current (I
off
).
For high speed operation of microelectronic components, circuit designers prefer transistors tuned for high drive currents. On the other hand, low leakage, i.e., low off-state current, is preferred so as to reduce power consumption. Typically, the structural and doping parameters that tend to provide the desired increase in drive current also tend to provide an undesired increase in leakage current. Use of metal gates will tend to improve drive current performance by reducing or eliminating the poly depletion effect. Unfortunately, many metals, while reducing or eliminating the poly depletion effect when used to form a gate electrode, will undesirably result in increased leakage current because the work function of that metal gate is not appropriate for providing the desired transistor threshold voltage.
What is needed are structures and methods for obtaining the desired electrical performance from insulated gate field effect transistors.
Additionally what is needed are structures suited for complementary metal oxide semiconductor (CMOS) integrated circuits, and methods of making such integrated circuits that are suitable for integration into a manufacturing process.
SUMMARY OF THE INVENTION
Briefly, a method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of conductive material.
In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal.
REFERENCES:
patent: 6028339 (2000-02-01), Frenette et al.
patent: 6091120 (2000-07-01), Yeom et al.
patent: 6140688 (2000-10-01), Gardner et al.
patent: 6171910 (2001-01-01), Hobbs et al.
Liang Chunlin
Zheng Jun-Fei
Fourson George
Garcia Joannie Adelle
Intel Corporation
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