Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2001-12-04
2004-03-30
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S436000, C257S760000
Reexamination Certificate
active
06713831
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method and device including the formation of a borderless contact structure.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. For example, after implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas have been defined upon the substrate, alternating levels of interlevel dielectric and interconnect lines may be placed across the semiconductor topography to form a multi-level integrated circuit. Such a multi-level integrated circuit may include a plurality of layers and structures. For example, contact structures and/or vias may be formed within interlevel dielectric layers and in connection with interconnect lines. In some embodiments, the interlevel dielectric layers may include doped oxides. In particular, doped oxides may be used for forming self-aligned contact structures due to their etch selectivity to other materials. However, doped oxides typically need to be protected from the environment of the semiconductor fabrication process to prevent the formation of crystals within the doped oxide layer. As such, a semiconductor topography including a doped oxide interlevel dielectric typically includes a cap layer deposited thereon.
Forming various structures of an integrated circuit sometimes involves selectively removing portions of a material while other materials remain intact. In some cases, the formation of such structures involves patterning a photoresist upon the material. In such an embodiment, the photoresist may be patterned such that structures of particular dimensions may be fabricated. However, the use of a photoresist upon a layer or structure including a highly reflective material, such as metal, may cause problems. In particular, optical energy rays reflected off the upper surface of a metal layer may undesirably widen the pattern of the photoresist by exposing additional portions of the photoresist. In addition or alternatively, the reflected energy rays may produce standing waves within the photoresist during exposure and result in an undesirably ragged post-develop photoresist profile. Such pattern issues may be particularly prevalent in sub-micron technologies.
Furthermore, the use of a photoresist above a nonplanar topography may cause problems due to the different reflective characteristics of the underlying steps and structures. More specifically, correctly patterning layers upon a topological surface containing elevational “hill” or “valley” areas may be difficult using optical lithography since the all parts of the topography must be within the depth of focus of the lithography system. As such, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. Furthermore, the resolution of sub-micron (i.e., 1.0 micron or less) images may be particularly difficult, since the depth of focus required to pattern an upper surface of a semiconductor topography using a lithography tool of a particular wavelength may decrease with reductions in feature size.
To address these problems, an anti-reflective coating (ARC) may be formed beneath the photoresist to minimize the reflection of energy back toward the energy source during exposure of the photoresist. As such, a more accurate patterned photoresist profile may be formed. In addition, the ARC may planarize the topography such that the photoresist may be subsequently formed upon a planar surface. In this manner, lithography equipment may be used to a single depth of focus, thereby minimizing the distortions of the patterned image. Subsequent to the removal of the exposed portion of the underlying material, the ARC may be removed along with the photoresist such that additional layers and structures may be formed.
One example of a structure that may be formed within an integrated circuit is a borderless contact structure. A borderless contact structure may be referred to as a contact structure with a width greater than the width of the interconnect line over which it is formed. Such structures may also be referred to as “unlanded contacts” or “negative enclosure contacts”. In order to form such a structure, a dielectric layer may be deposited upon an interconnect line and a trench with a width greater than the interconnect line may be etched within the dielectric layer to expose a portion of the interconnect line. The trench may be thereafter filled and planarized to form a borderless contact structure.
In some embodiments, the borderless contact structure may extend below the upper surface of the interconnect line. For example, the contact structure may extend along one or more sides of the interconnect line when the depth of the trench extends below the upper surface of the interconnect line. In some cases, the depth of the trench (and thus the borderless contact structure) may extend beyond the lower surface of the interconnect line into underlying portions of the semiconductor topography. Such an extension of a contact structure, generally referred to as punchthrough, may cause reliability issues and/or cause a device to be inoperable. As such, an etch stop layer may be formed above or below the interconnect line prior to formation of the trench such that the borderless contact structure does not extend into underlying portions of the semiconductor topography. Typically, such an etch stop layer includes silicon nitride since it adheres well to many materials and has good etch selectivity as compared to oxide. The use of such an etch stop layer, however, undesirably increases the process cycle time and fabrication costs of the device.
It would, therefore, be advantageous to develop a method for forming a borderless contact structure with fewer processing steps and layers.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a method for processing a semiconductor substrate. In particular, a method is provided which includes using an inorganic anti-reflective coating (IARC) layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in this embodiment, which includes an IARC layer arranged below an interconnect line. Such a topography may further include a contact structure with a width greater than the width of the interconnect line and arranged upon the interconnect line.
As stated above, the method described herein may include using an IARC layer as an etch stop to form a borderless contact structure. The use of such an IARC layer may include depositing an interlevel dielectric layer above the IARC layer and etching a trench within the interlevel dielectric layer. The etching process may be terminated upon exposure of the IARC layer. The borderless contact structure may then be formed in contact with the interconnect line by filling the trench with a conductive material. In a preferred embodiment, the method may include using the IARC layer as a pattern layer for an underlying interlevel dielectric layer prior to using the IARC layer as an etch stop. More specifically, the method may include depositing the IARC layer upon the interlevel dielectric layer and depositing a photoresist layer upon the IARC layer. The method may further include patterning the photoreisist layer and IARC layer to expose portions of the interlevel dielectric layer. Alternatively, the photoresist layer may be patterned to exposed por
Ben-Tzur Mira
Chowdhury Saurabh Dutta
Fastow Michal E.
Sadoughi Sharmin
Brophy Jamie L.
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin J.
Zarabian Amir
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