Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-03
2004-08-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S167000, C438S530000, C438S542000, C438S543000
Reexamination Certificate
active
06770519
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor apparatus manufacturing method. In particular, it relates to annealing required for impurity diffusion and activation processes.
2. Description of the Related Art
In recent years, the improvement of Large Scale Integrated Circuit (LSI) performance has been achieved by enhancing the integrated density, that is, by miniaturizing the elements used to configure an LSI. However, accompanying the miniaturization of elements, since parasitic resistance or a short channel effect may occur more easily, it has become important to form shallow p-n junctions with low resistance in order to prevent such occurrence.
As a method of forming the shallow p-n junction, that is, a shallow impurity diffusion layer, which is a source/drain region, in a well, performing ion implantation at low acceleration energy and shortening the subsequent annealing processing (heat treatment) is typically utilized for adjusting the diffusion depth to be shallow. For example a Rapid Thermal Anneal (RTA), which is performed in a matter of seconds using a halogen lamp is utilized as a short-time annealing method.
Nevertheless, calls are being made for even shallower p-n junction depths in addition to demands for miniaturization, and it appears as if it is necessary to form extremely shallow junctions of less than 20 nm. At present, although boron (B) is mainly used as the p-type impurity, and phosphorus (P) or arsenic (As) as the n-type impurity, it is difficult to form extremely shallow p-n junction depths under 20 nm even by adopting RTA since the diffusion factor of the impurity such as boron, phosphorus, or arsenic is relatively high in a silicon (Si) substrate.
In addition, in the case of using a halogen lamp, it is difficult to adjust the illuminating time to be several hundred ms or shorter, and there is a limit to how much the annealing time can be reduced. Meanwhile, when the annealing temperature, that is, the luminous energy intensity is lowered in order to control impurity diffusion, the activation rate of the impurity declines drastically, and resistance in the impurity diffusion layer rises. Accordingly, it is difficult to form a shallow impurity diffusion layer with a depth of less than 20 nm with low resistance through RTA processing using a halogen lamp.
Recently, a flash-lamp annealing method using a xenon (Xe) flash lamp has been considered by the inventers of the present invention in place of the conventional RTA processing method using a halogen lamp. The xenon flash lamp is a white light having a wide range light-emitting wavelength, from the visible region to near-infrared region, and is a light source capable of illuminating for extremely short time periods of several 100 &mgr;m to 10 ms. It becomes possible to perform instantaneous annealing at high temperatures by adopting this flash-lamp annealing method using the xenon flash lamp. As a result, it is possible to activate the impurity and form a shallow p-n junction with low resistance without causing diffusion of the ion-implanted impurity.
Typically, in the manufacturing process of a MOS transistor using a polycrystal silicon gate electrode, which is called a poly-Si gate, when an impurity is ion-implanted into a semiconductor substrate, the impurity is also ion-implanted into the gate electrode in order to lower the resistance of the gate electrode. Resistance is then lowered by activating the impurity implanted in the semiconductor substrate, in addition to diffusing the impurity in the gate electrode layer throughout the gate electrode and causing activation through the annealing process.
Since the emission time of the lamp is extremely short in the annealing method that uses a xenon flash lamp, extremely short time annealing treatment is possible, and since the impurity in the semiconductor substrate is activated without causing diffusion, it is possible to form a shallow source/drain region. However, since annealing time is extremely short, the implanted impurity may not be diffused throughout the gate electrode, and a region where impurity diffusion is unsatisfactory may remain in the gate electrode. This unsatisfactory impurity region becomes depleted, causing a lowering of capacitance, which as a result invites a drop in the driving force of the transistor.
Accordingly, the annealing method using a xenon flash lamp may form an impurity diffusion layer, which is a source/drain region, with low resistance and a shallow junction, however, since a depletion layer remains in the gate electrode, even if a microscopic transistor is formed, high performance transistor characteristics with the miniaturized elements accompanying miniaturization may not be obtained.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a method of manufacturing a semiconductor device includes forming a gate insulating layer upon a single clystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting an impurity in the gate electrode and in the surface layer of the semiconductor substrate adjacent to or separate from the gate electrode, performing a first heat treatment, and performing a second heat treatment. Here, the first heat treatment performs heat treatment at a temperature that diffuses the impurity implanted mainly in the gate electrode and controls the diffusion of the impurity implanted in the surface layer of the semiconductor substrate. The second heat treatment performs at a higher temperature and for a shorter time than the first heat treatment, and at a temperature that activates the impurity implanted in the semiconductor substrate.
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Ito Takayuki
Suguro Kyoichi
Everhart Caridad
Kabushiki Kaisha Toshiba
Luu Chuong A
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