Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-23
2004-03-30
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S157000, C438S424000, C438S738000
Reexamination Certificate
active
06713356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device comprising a stack of silicon layers alternating with dielectric material layers. It has a particularly beneficial application in applications such as ultimate CMOS, the integration of logic functions into a single structure, memories, gate all around (GAA) transistors, sensors, etc.
2. Description of the Related Art
One limiting factor of a standard massive architecture MOSFET is the substrate effect which degrades the performance of the transistor. This drawback is avoided in a silicon on insulator (SOI) architecture MOSFET by separating the thin film of silicon from the substrate by means of a buried layer of silicon oxide.
Eliminating the substrate effect in a totally depleted thin-film SOI architecture MOSFET increases the drain current.
However, an ultrathin SOI architecture MOSFET has a high source/drain (S/D) resistance because of shallow junctions limited by the thickness of the silicon layer and poor thermal conductivity. The cost of fabricating SOI architecture substrates is also high, which has restricted their entry onto the market.
Silicon on nothing (SON) architecture transistors combining the advantages of the massive and silicon on insulation (SOI) architectures can eliminate the above disadvantages.
FIG. 1
shows an SON architecture transistor comprising a silicon substrate
1
having a top surface coated with a thin gate dielectric layer
4
and in which source and drain regions
5
and
6
, which define a channel region
1
a
between them, and a gate
7
on the top surface of the body above the channel region
1
a
are formed. The channel region
1
a
of the transistor between the source and drain regions
5
and
6
further includes a continuous insulative cavity
2
delimiting, in conjunction with the drain and source regions
5
and
6
, a thin layer
3
of silicon on top of the insulative cavity
2
. The gate
7
has spacers
8
and
9
on either side. Contacts
10
,
11
are provided in the source and drain regions
5
,
6
.
A method of producing a basic semiconductor device, from which the transistor described above can be made, may be desirable.
A method of making ultimate CMOS integrating logic functions into a single structure, memories, gate all around (GAA) transistors, sensors, etc, in which the substrate effect is eliminated or at least reduced without increasing the series resistance of the source and drain regions may also be desirable. The method may offer improved heat dissipation over SOI architecture devices and have fabrication costs lower than those of the SOI architecture.
SUMMARY OF THE INVENTION
In an embodiment, a method of fabricating a semiconductor device includes the following steps:
a) forming on a main surface of a silicon substrate, a stack having successively at least one first combination and one second combination. Each combination having, with reference to the substrate, a thin bottom layer of germanium, or a germanium and silicon alloy (SiGe), and a thin top layer of silicon;
b) forming on the thin top silicon layer of the second combination, a thin silicon dioxide layer that supports the layers of the stack on at least two opposite lateral sides of the stack;
c) forming a hard mask on the thin silicon dioxide layer so as to form two separate opposed areas on respective opposite sides of two opposite edges of the hard mask;
d) etching the thin silicon dioxide layer, the top silicon layer, and at least part of the lower germanium or SiGe layer of the second combination in the two separate opposed areas;
e) selectively laterally etching the bottom germanium or SiGe layer of the second combination to form a tunnel;
f) filling the tunnel of the second combination with a solid dielectric material;
g) etching the top silicon layer and at least part of the bottom germanium or SiGe layer of the first combination in the two separate opposed areas;
h) selectively laterally etching the bottom germanium or SiGe layer of the first combination to form a tunnel; and
i) optionally filling the tunnel of the first combination with a solid dielectric material.
The germanium and silicon alloys (SiGe) may include alloys with the formulas Si
1-x
Ge
x
(0<x≦1) and Si
1-x-y
Ge
x
C
y
(0<x≦0.95; 0<y≦0.05).
The hard mask can be made from any conventional material, which can be selectively etched relative to silicon, germanium, and/or SiGe.
The etching of the separate opposed areas of steps d) and g) may include plasma etching, which is well known in the art.
The etching of the germanium or SiGe layers of steps e) and h) is either anisotropic plasma etching, which is selective relative to silicon and the dielectric material, or selective chemical etching using an oxidizing solution, which is well known in the art. The tunnels formed in this way, in place of the germanium or SiGe layers, are filled with a solid dielectric material during steps f) and i). For example, the tunnels are filled with silicon dioxide (SiO
2
) or Ta
2
O
5
. In particular, they can be filled with SiO
2
by thermal oxidation. Nevertheless, the tunnel of the first combination need not be filled with a solid dielectric material, in which case air is used as the dielectric material for that tunnel, without compromising the physical integrity of the semiconductor device obtained.
In an embodiment, a semiconductor device includes a silicon body on part of which is formed a stack of successive layers of dielectric material and silicon.
In an embodiment, the dielectric material layer of the stack immediately adjacent the silicon body is a layer of air. The upper layers may be supported by the final silicon dioxide layer extending beyond the stack on two opposite lateral sides.
REFERENCES:
patent: 6495403 (2002-12-01), Skotnicki et al.
patent: 6537894 (2003-03-01), Skotnicki et al.
patent: 6555482 (2003-04-01), Skotnicki et al.
patent: 0 539 685 (1993-05-01), None
patent: 96/15550 (1996-05-01), None
patent: 97/23000 (1997-06-01), None
M. Jurczak et al: “SON (Silicon On Nothing)-A New Device Architecture for the ULSI Era” 1999 Symposium on VLSI Technology Digest of Technical Papers (IEEE CAT. No. 99CH36325), Proceedings from the 1999 Symposium on VLSI Technology, Kyoto, Japan, Jun. 14-16, 1999, pp. 29-30, XP002133376, 1999, Tokyo, Japan, Japan Soc. Appl. Phys, Japan ISBN: 4-930813-93-X.
Jurczak Malgorzata
Skotnicki Thomas
France Telecom
Luhrs Michael K.
Meyertons Eric B.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Nguyen Van Thu
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