Phase-controlled source synchronous interface circuit

Details Phase-controlled source synchronous interface circuit Phase-controlled source synchronous interface circuit

2001-03-02

2004-11-02

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C327S149000

Reexamination Certificate

active

06813724

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a circuit technique for passing data signals between a plurality of logic circuits and in particular, to a technique applicable even when a transmission delay of the data signals greatly varies, i.e., a technique for adjusting the delay time and adjusting the phase upon signal reception to a desired value, thereby realizing a normal transmission.
In a logic circuit apparatus such as a computer, a plurality of logic circuits are synchronized with a single system clock when passing data signals between logic circuits in the apparatus.
To operate these circuits normally, data signals transmitted should reach a predetermined destination within a desired time. Such a transmission technique is disclosed, for example, in WO096/29655 laid open on Sep. 26, 1996.
FIG. 13
shows an example of this convention data signal transmission method for transmitting data signals between logic circuits.
In
FIG. 13
, a reference symbol
1301
denotes a logic circuit for transmitting a signal and
1304
denotes a logic circuit for receiving the signal. A flip-flop
1304
takes in an output from the other circuit block
1303
in the logical circuit
1301
in synchronization with a system clock SCK. A resultant data signal is transmitted via a driver
1305
to a data transmission line
1306
. A data signal received at a receiver
1307
of the logic circuit
1302
is fed to a flip-flop
1309
operating in synchronization with the system clock SCK and then transmitted to the other circuit block in the logic circuit
1302
.
FIG. 14
shows a timing relationship of this transmission: a signal SCK is a system clock signal; a signal D
1
is an output signal from the flip-flop
1304
; a signal D
2
is an input signal to the flip-flop; and a signal D
6
is an output signal from
1309
.
As shown in this figure, for example, in order that output of a signal D
2
to the flip-flop
1304
be accompanied by output of a signal D
6
with a delay of two system clock cycles, it is necessary to design delay time values of the flip-flop
1304
, the driver
1305
, the data transmission line
1306
, the receiver
1307
, and the flip-flop
1309
, so as to satisfy a formula below:
Tck<Td<
2
×Tck
  (1)
wherein Tck represents the system clock cycle and Td represents a delay time from the signal D
2
to D
3
(including the delay time of the flip-flop).
However, this conventional example has a problem that the delay time values of the respective circuits or the data transmission line
1306
may fluctuate due to the production process fluctuation, disabling a normal data signall transmission.
FIG. 15
shows a case when the delay time Td is changed to increase &Dgr;Td.
In this case, as shown in the figure, the input data signal D
2
of the flip-flop has a phase almost matched with a phase of the system clock signal SCK. For this, the flip-flop
1309
cannot assure a setup time required for correctly receive the data (time required for correcting receiving the data, i.e., a period of time between the moment when the data signal value is identified and the moment when the system clock signal is input) or hold time (time required for correctly receiving the data, i.e., a period of time for maintaining the data signal at a constant value after the input of the system clock signal). The output data signal has a logical value not defined to be “0” or “1”, i.e., in a meta-stable state as described in the conventional example, disabling to correctly perform a signal transmission.
To evade this, as shown in the conventional example, it is necessary to arrange a plurality of stages of flip-flop at the later stage of the flip-flop
1309
, so as to synchronize the data signal. This increases the signal transmission time, adversely affecting the high-speed technique.
To solve the problem that the fluctuation of data transmission time between the logic circuits disables a correct transmission, for example, the aforementioned Patent Publication WO96/29655 discloses a source synchronous system for transmitting a clock signal in parallel with a data signal to be transmitted from a transmission side to a reception side.
FIG. 16
shows the principle of this conventional source synchronous system.
A flip-flop
1604
is supplied with an output from other circuit block
1603
in a logic circuit
1601
in synchronization with a system clock SCK. A resultant data signal is transmitted via a driver
1605
to a data transmission line
1606
. Moreover, the logic circuit
1601
includes a source synchronous clock generator for generating a source synchronous clock signal DCK from a system clock SCK and a driver
1613
for transmitting the source synchronous clock signal DCK to a clock transmission line. In a logic circuit
1602
of the reception side, the source synchronous clock signal DCK is received by a receiver
1615
is distributed via a distributor
1616
to a flip-flop
1608
. In synchronization with this source synchronous clock signal DCK distributed, the flip-flop
1608
takes in the data received by a receiver
1607
. An output from the flip-flop
1608
is supplied to a flip-flop
1609
which is in synchronization with the system clock SCK. That is, the logical level is decided at the timing synchronized with the system clock SCK and held before supplied to the other circuit block
1610
.
FIG. 17
shows a relationship of a data transmission timing relationship in this source synchronous system.
A signal SCK is a system clock; a signal D
2
is an output signal from the flip-flop
1604
; a signal D
3
is an input signal to the flip-flop
1608
; a signal D
4
is an output signal from
1608
, which is an input signal to the flip-flop
1609
; and a signal D
6
is an output signal from
1609
. A signal C
4
is an output signal from the source synchronous clock generator; a signal C
5
is an input signal to a clock distributor; and a signal C
6
is a source synchronous clock signal supplied to the flip-flop
1608
.
In this method, as shown in Formula 2 below, a delay time Td of a data signal from the output of the flip-flop
1604
to the input of the flip-flop
1608
(including a delay time of the flip-flop
1604
) is approximately identical to a delay time Tc1 from the output of the source synchronous clock generator
1612
to the input of the clock distributor
1616
(including a delay time of the generator
1612
) because the length of wiring
1606
for a data signal is designed to be approximately equal to the length of wiring
1614
for the source synchronous clock signal DCK.
Td≈Tc1  (2)
Consequently, when the delay time Tc2 from the input of the clock distributor
1616
to the flip-flop
1608
is designed to be about ½ of the system clock cycle Tck, as shown in this figure, the flip-flop
1608
can normally receive the data signal D
2
and the data signal D
3
received by the flip-flop
1608
can be received like the data signal D
4
by the flip-flop
1609
.
According to this method, Formula 2 is always satisfied approximately because even when delay time values of the respective circuits
1604
,
1605
,
1607
,
1612
,
1613
, and
1615
or delay time values of the data transmission line
1606
and the clock transmission line
1614
fluctuate because of the production process irregularities, the delay time values fluctuate in the same direction thanks to the effect of the aforementioned design.
Accordingly, to transmit data between the logic circuits, what is necessary is to design the delay time values of
1604
,
1605
,
1606
,
1607
,
1612
,
1613
,
1614
, and
1615
so as to satisfy Formula 2.
However, even in this conventional source synchronous system, there is a case when a correct signal transmission cannot be performed.
FIG. 18
shows a case when the delay time Td and the Tc1 in
FIG. 16
are shifted to be increased by &Dgr;Td and &Dgr;Tc1, respectively. In this case also, Formula below is satisfied
Td+&Dgr;Td≈Tc
1
+&Dgr;Tc
1  (3)
and the flip-flop
1608
can normally receive the data signal D
2
.
However, i

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