Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2002-09-30
2004-12-14
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S787000, C257S666000, C257S693000
Reexamination Certificate
active
06831372
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to electronic devices with semiconductor chips and a leadframe with device positions and to methods for producing the same.
Semiconductor chips with contact areas on their active top sides, which have integrated circuits, are disposed on chip islands of leadframes and their contact areas are connected to contact pads or bonding fingers on corresponding inner flat conductor sections of the leadframe via connecting lines. The inner flat conductor sections with their contact pads serve to create a transition from the microscopically small contact areas of a semiconductor chip to macroscopic output terminals of the electronic device. In this connection, “microscopically small” is to be understood as dimensions in the micrometer range that can be measured with the aid of a light microscope. By contrast, “macroscopic structures” can already be discerned and measured with the naked eye.
The chip island serves to receive a semiconductor chip of predetermined size and to connect the rear side of the semiconductor chip to the potential of the chip island via an electrically conductive adhesive layer. However, in production, after functional testing, failures occur in which the potential of the chip island is not present at the rear side of the semiconductor chip.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide electronic devices with semiconductor chips and a leadframe with device positions and methods for producing the same that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that reduce failures creates a reliable electrical connection for the rear side of the semiconductor chip, and enables semiconductor chips of different size to be mounted and reliably contact-connected on a chip island of unchanged size.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an electronic device and a lead-frame, having a semiconductor chip, which is disposed with its rear side on a chip island. On its top side, the semiconductor chip has contact areas electrically connected to contact pads of the chip island or to contact pads of inner flat conductor sections. The chip island has a coplanar pattern of electrically conductive contact layer regions alternating with insulating adhesion layer regions at least in the region of the chip island that is covered by the semiconductor chip.
Such a coating below the adhesive layer of the semi-conductor chip and directly on the metallic surface of the chip island has reduces the failures during the testing of the finished electronic devices. This novel intermediate layer includes a coplanar pattern of electrically conductive contact layer regions and insulating adhesion layer regions below the adhesive layer with which the semiconductor chip is fixed on the metallic surface of the chip island. The intermediate layer has been able to successfully reduce the migration of filling material of the conductive adhesive layer into the copper surface of the leadframe and at the same time improve the adhesion of the adhesive layer by the insulating adhesion layer regions.
Consequently, it has been possible to eliminate the cause—determined after intensive investigations—of the migration of a conductive filling material to the copper surface and an associated depletion of filling material in the conductive adhesive. Although the insulating adhesion layer regions on the chip island reduce the contact layer of the conductive adhesive, the increase in the contact resistance in these adhesion layer regions has been able to be compensated for by the improved contact of the conductive adhesive in the contact layer regions.
Both the contact layer regions and the adhesion layer regions of the coplanar pattern on the chip island successfully prevent the migration of the electrically conductive filling material of the conductive adhesive in the direction of the metal surface of the chip island. Furthermore, the adhesion layer regions on the chip island provide for an intensive anchoring of the conductive adhesive and thus for an intensive anchoring of the semiconductor chip on the chip island. The combined application of contact layer regions and adhesion layer regions as coplanar pattern on the chip island thus ensures that the rear side of the semi-conductor chip is reliably connected to the electrical potential of the chip island.
In one embodiment of the invention, the pattern has a chessboard pattern. Such a chessboard pattern has the advantage that the semiconductor chip on the chip island can be miniaturized as desired and can be shrunk in its size, without immediately having to construct a new housing and a new substrate carrier with an adapted chip island, since a surface-size-independent anchoring of the electrically conductive adhesive is ensured by the chessboard-like adhesion layer regions and, on the other hand, a sufficient size-independent contact-making and connection between rear side of the semi-conductor chip and chip island is likewise ensured by the chessboard-like contact layer regions.
Instead of the chessboard pattern, the coplanar pattern on the chip island may also have a strip pattern. A strip pattern is also associated with the advantage that the size of the chip can be miniaturized as desired, without reducing the chip island size.
Instead of the strip pattern or the chessboard pattern, further embodiments of the invention provide rhomboid patterns or annular patterns, which have a similar advantage to chessboard patterns and strip patterns.
In a further embodiment of the invention, the contact layer regions have an electrodeposited metal alloy plating. This electrodeposited metal alloy plating is not covered by the insulating adhesion layer at the contact layer regions, so that the contact layer regions of the coplanar pattern are electrically connected to the conductive adhesive for the semi-conductor chip on the chip island. Such an electro-deposited plating has the advantage that it can be applied in a large-area manner both on the chip island and on inner flat conductor sections and can subsequently be structured by a selective covering in the adhesion layer regions to form the pattern according to the invention.
In a further embodiment of the invention, the metal alloy plating has aluminum, silver, gold, or alloys thereof. These metals are accumulated by the contact layer regions in such a concentrated manner on the metallic top side of the chip island that a depletion of conductive solid material formed from metal particles in the adhesive cannot take place. In addition, the metallic filling material for the conductive adhesive can be coordinated with the contact layer material. Thus, it is advantageous, in the case of a silver particle filling of the adhesive, for the contact layer regions likewise to be produced from an electro-deposited silver layer in order thus to prevent the migration of silver to the metallic surface of the chip island, which may be composed of copper or copper alloy.
On account of the selectively provided adhesion layer, the surface of the electrodeposited metal alloy plating remains freely accessible for a connection to connecting lines, i.e. the metal alloy plating is kept free of the adhesion layer both below the semiconductor chip and on inner flat conductor sections, in order to ensure both a connection of the contact layer regions to bonding wire lines and a connection of the rear side of the semiconductor chip to the potential of the chip island. Although the adhesion layer includes materials that hinder an electrical connection, contact layer regions are also provided below the semiconductor chip on the inner flat conductors and on the chip island, which contact layer regions are refined with a connect-able coating and ensure an electrical contact-connection.
In a further embodiment of the invention, the adhesion layer has a metal oxide layer. Such metal oxide layers are electrically nonconduct
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