Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-11-27
2004-04-06
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S001000, C375S371000, C375S356000, C375S354000
Reexamination Certificate
active
06718476
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of data bus systems. More particularly, the present invention relates to the field of synchronizing local clocks in a data bus system.
2. Related Art
The 1394 Serial Bus Standard (or 1394 Standard) is a protocol for a high performance digital serial data bus. The 1394 Standard provides a versatile, high-speed method of interconnecting a variety of devices (e.g., computer system, digital camera, digital VCR, TV settop box, digital camcorder, storage device, digital audio device, etc.). Moreover, the 1394 Standard enables a wide range of applications, including desktop video editing, publishing, data storage, video conferencing, and home Audio/Video networking. Rapid embrace of the 1394 Standard has been spurred by the emergence of digital video and multimedia applications.
The 1394 Standard offers many advantages over other technologies. The major advantages include very high speed data transfer rates, self-configuring, plug-and-play operation, both asynchronous data transfer (guaranteed delivery) and isochronous data transfer (guaranteed bandwidth with low overhead), and flexible topology.
The 1394 Standard was originally adopted in 1995 as the 1394-1995 specification. Later, the original specification was revised, providing some clarification on the original specification, changing some optional portions of the original specification to mandatory, and adding some performance enhancements. The first revision was approved and is known as the 1394a specification. A second revision of the 1394 Standard is known as the 1394b specification. The 1394b specification represents a significant enhancement of the 1394 Standard.
FIG. 1
illustrates the well-known protocol layers of the 1394 Standard, whereas each device compliant with the 1394 Standard implements the protocol layers. The 1394 Standard includes a transaction layer
20
, a link layer
30
, a physical layer
40
, and a serial bus management layer
60
. The protocol layers interact and interface with the host
10
(e.g., processor, PCI Bus, application, etc.) and with the 1394 connector, whereas the 1394 connector physically couples one device to another device. Each protocol layer is implemented as circuitry, software, or both.
The physical layer
40
is responsible for the clocking scheme of the 1394 Standard. The physical layer
40
maintains a local clock, whereas each device has a respective local clock. Data transmissions from a transmitting device to a receiving device are synchronized by the local clock of the transmitting device. The transmitting device transmits data and its local clock to the receiving device. The receiving device recovers the local clock of the transmitting device and utilizes the recovered local clock to recover the data transmitted by the transmitting device.
FIG. 2
illustrates a conventional 1394b data bus system
200
according to the prior art, showing the conventional clocking scheme of the prior art. The conventional 1394b data bus system
200
includes a plurality of nodes
210
A-
210
F. Each node is a device (e.g., computer system, digital camera, digital VCR, TV settop box, digital camcorder, storage device, digital audio device, etc.) which is compliant with the 1394b specification. One of the plurality of nodes is designated as a root node according to the 1394b specification. Here, node A
210
A is the root node
210
A.
Each node
210
A-
210
F includes an oscillator
215
A-
215
F for generating a respective local clock
220
A-
220
F or CLK A-CLK F, whereas each local clock
220
A-
220
F operates at a nominal frequency of 25 MHz. Moreover, each node
210
A-
210
F includes a cycle counter
230
A-
230
F for coordinating time dependent data (e.g., digital video data, digital audio data, etc.). Each cycle counter
230
A-
230
F is incremented by a respective local clock
220
A-
220
F. In addition, each node
210
A-
210
F includes a buffer
240
A-
240
F for storing data which is to be transmitted to another node or which has been received from another node.
Node A
210
A includes a port
262
A coupled to a phase locked loop
252
A, a port
264
A coupled to a phase locked loop
254
A, and a port
266
A coupled to a phase locked loop
256
A. Node B
210
B includes a port
262
B coupled to a phase locked loop
252
B and a port
264
B coupled to a phase locked loop
254
B. Node C
210
C includes a port
262
C coupled to a phase locked loop
252
C. Node D
210
D includes a port
262
D coupled to a phase locked loop
252
D. Node E
210
E includes a port
262
E coupled to a phase locked loop
252
E and a port
264
E coupled to a phase locked loop
254
E. Node F
210
F includes a port
262
F coupled to a phase locked loop
252
F.
According to the 1394b specification, each node
210
A-
210
F assigns a parent port identifier (illustrated by “P”) to a port to indicate that a node which is closer to the root node
210
A is coupled to that port. Moreover, each node
210
A-
210
F assigns a child port identifier (illustrated by “C”) to a port to indicate that a node which is farther away from the root node
210
A is coupled to that port. For example, the port
262
B of node B
210
B is a parent port because port
262
B is coupled to node A
210
A, which is a node that is actually the root node
210
A. Similarly, the port
262
C of node C
210
C is a parent port because port
262
C is coupled to node B
210
B, which is a node that is closer to the root node
210
A. Moreover, the port
262
A of node A
210
A (the root node) is a child port because port
262
A is coupled to node B
210
B, which is a node that is farther from the root node
210
A. Similarly, the port
264
B of node B
210
B is a child port because port
264
B is coupled to node C
210
C, which is a node that is farther from the root node
210
A.
Node A
210
A transmits data via data connections
271
,
276
, and
278
. Node B
210
B transmits data via data connections
272
and
273
. Node C
210
C transmits data via data connection
274
. Node D
210
D transmits data via data connection
275
. Node E
210
E transmits data via data connections
277
and
270
. Node F
210
F transmits data via data connection
279
. Each data connection
270
-
279
is a twisted wire pair.
According to the 1394b specification, a transmitting node (e.g., node A
210
A) uses its local clock (e.g., CLK A) to synchronize transmission of data packets to the receiving node (e.g., node B
210
B) via a data connection (e.g., data connection
271
). The transmitting node (e.g., node A
210
A) encodes on a single twisted wire pair (e.g., data connection
271
) the data packets and its local clock (e.g., CLK A) using a
8
B
10
B coding. The receiving node (e.g., node B
210
B) utilizes a phase locked loop (e.g., phase locked loop
252
B) (which is coupled to the port that is coupled to the transmitting node) to recover the local clock (e.g., CLK A) of the transmitting node (e.g., node A
210
A). The receiving node (e.g., node B
210
B) utilizes the recovered local clock (e.g., CLK A) to recover the data packets transmitted via a data connection (e.g., data connection
271
). If the receiving node (e.g., node B
210
B) retransmits the data packets to another node (e.g., node C
210
C), the receiving/retransmitting node (e.g., node B
210
B) uses its local clock (e.g., CLK B) to synchronize transmission of data packets to a second receiving node (e.g., node C
210
C) via a data connection (e.g., data connection
273
). The receiving/retransmitting node (e.g., node B
210
B) encodes on a single twisted wire pair (e.g., data connection
273
) the data packets and its local clock (e.g., CLK B).using a
8
B
10
B coding. The second receiving node (e.g., node C
210
C) utilizes a phase locked loop (e.g., phase locked loop
252
C) (which is coupled to the port that is coupled to the receiving/retransmitting node) to recover the local clock (e.g., CLK B) of the receiving/retransmitting node (e.g., node B
210
B). The second receiving node (e.g., node C
210
C) utilizes the re
Connolly Mark
Lee Thomas
Sony Corporation
Wagner , Murabito & Hao LLP
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