Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-11-10
2004-10-05
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S644000, C438S654000, C438S674000
Reexamination Certificate
active
06800549
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods for fabricating the same. More specifically, the present invention is directed to semiconductor devices including a via contact hole connecting upper and lower layers of multi-level interconnections and methods for fabricating the same.
BACKGROUND OF THE INVENTION
With ever higher integration density in semiconductor devices, interconnections become increasingly complicated. Since it is difficult to form such complicated interconnections into a single layer, multi-level interconnections formed of a plurality of layers are primarily used. Aluminum has become a popular material for interconnections of semiconductor devices, since it offers many advantages. However, since aluminum interconnections are generally formed by sputtering, it is difficult to fill a contact hole of a high aspect ratio with aluminum. At the same time, aluminum suffers from the serious shortcoming of cutting caused by electro-migration. Also, as integration increases, the width of metal interconnections and the width of contacts are reduced. For this reason, interconnection resistance and a contact resistance are increased.
Copper has been proposed as an interconnection material for semiconductor devices, as a material that enables minimization of the interconnection and contact resistances. Copper interconnections, the resistance of which is lower than that of aluminum interconnections, may decrease interconnection resistance, and may alleviate cutting caused by electro-migration, in order to thereby improve reliability. However, it is difficult to apply a patterning process to copper interconnections by etching. In addition, copper is easily diffused into a silicon layer and silicon oxide layer, thereby increasing current leakage and parasitic capacitance.
A variety of methods have been developed to solve the foregoing problems. First, a damascene process was proposed to overcome the difficulty of patterning. In the case of the damascene process, to begin with, a lower insulation layer is etched to form a groove therein. A copper layer is then stacked on the resultant structure and is planarizingly etched using chemical-mechanical polishing (CMP) until a top surface of the lower insulation layer is exposed. As a result, the copper remains only in the groove to form interconnections. It is therefore unnecessary to directly pattern the copper. Diffusion of copper may be prevented by using a barrier layer composed of a conductive layer or an insulation layer.
Meanwhile, a conductive barrier layer, referred to as a “barrier metal” among barrier layers may be used for processes of fabricating interconnections using not only copper but also gold or silver, which are also low-resistance metals suitable for interconnections. In addition, the conductive barrier layer has been widely used to fabricate aluminum or tungsten contact plugs, in order to prevent a spike phenomenon.
FIG. 1
is a cross-sectional view illustrating a step of forming a via contact in a semiconductor device with conventional multi-level interconnections. Referring to
FIG. 1
, a lower interconnection
13
is formed using a damascene process over a substrate
10
where a first interlayer dielectric (ILD)
11
is formed. An relatively thin insulating capping layer
15
is formed to serve as a barrier layer to prevent diffusion of copper on the lower interconnection
13
, and a second ILD
17
formed of an insulation layer, for example a silicon oxide layer, is stacked on the resultant structure. The capping layer
15
and the second ILD
17
are patterned to form a via contact hole that exposes the lower interconnection. A cleaning process is conducted to remove residue from a surface of the exposed lower interconnection
13
. While the capping layer
15
is etched and the surface of the lower interconnection
13
is cleaned, a portion of the copper layer may be also etched to form an undercut
25
under the capping layer
15
in the vicinity of the contact hole. A barrier metal
19
is then stacked on the substrate where the contact hole is formed. The barrier metal
19
covers an inner wall of the contact hole without filling the undercut
25
. At this time, the barrier metal
19
is stacked to a relatively greater thickness on a bottom of the contact hole. However, a minute gap between the lower interconnection
13
and the capping layer
15
, which is formed by the unfilled undercut
25
, intervenes between the barrier metal
19
and the lower interconnection
13
. After forming the barrier metal
19
, a copper layer
21
is stacked to form a via contact plug that fills the contact hole.
Here, the copper layer of the lower interconnection
13
and that of the contact plug
21
are electrically connected through a thick barrier metal
19
′ at the bottom of the contact plug as illustrated in FIG.
1
. While the barrier metal
19
is formed, the undercut
25
may become a void. The barrier metal
19
′ at the bottom of the contact plug is electrically connected in series with the contact plug and the lower interconnection
13
between the copper layers. The barrier metal
19
is typically composed of tantalum (Ta) or tantalum nitride (TaN) of which conductivity is lower than that of copper, thereby causing the resistance to be increased at an interface of the via contact. As the size of the contact is reduced as device integration increases, the density of current passing through the via or contact hole becomes higher than that at each interconnection. Therefore, a probability of cutting caused by electro-migration becomes higher at the via or contact. In particular, the electro-migration becomes an especially serious issue at the portion where contact plugs for connecting interconnections of each layer are vertically connected, because current crowding arises at these locations. At this portion, the barrier metal prevents connection between the copper layers of the contact plug and the lower interconnection. Therefore, a void is generated so as to elevate the probability of cutting.
SUMMARY OF THE INVENTION
The present invention addresses the limitations of the aforementioned approaches that are caused by the barrier metal that is used to form a contact plug for metal multi-level interconnections. It is therefore a feature of the present invention to provide a semiconductor device, where the metal of a lower interconnection and that of a via contact plug are in direct contact with each other, without a barrier layer therebetween, in at least a portion of the interface.
It is another feature of the present invention to provide a semiconductor device that is structured to decrease contact resistance and to prevent shortening of product life due to electro-and stress-migration in the vicinity of a contact interface, and a method for fabricating the same.
It is still another feature of the present invention to provide a semiconductor device that may extend the term of guarantee of products and improve product characteristics with a reduction in circuit resistance, and a method for fabricating the same.
In accordance with an aspect of the present invention, there is provided a semiconductor device comprising a lower metal interconnection having a copper layer, an interlayer dielectric (ILD) formed on the copper layer of the lower metal interconnection, and an upper metal interconnection formed on the ILD. The ILD includes lower and upper barrier layers that have an etch selectivity with respect to each other. The lower and upper metal interconnections are connected by a via contact plug that penetrates the ILD. The via contact plug comprises an inner copper layer. A portion of the via contact plug crossing the lower barrier layer is formed to have a greater width as compared to a portion crossing the upper barrier layer. A barrier metal layer is disposed on a sidewall of the via contact plug and on a portion of the bottom of the via contact plug. Namely, the barrier metal layer is composed of a first portion on the sidewall of the via contact plug
Brewster William M.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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