Semiconductor memory device having a trench and a gate...

Details Semiconductor memory device having a trench and a gate... Semiconductor memory device having a trench and a gate...

2003-03-19

2004-03-30

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S152000, C438S153000, C257S368000, C257S903000, C257S393000

Reexamination Certificate

active

06713345

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and fabrication method thereof.
2. Background of the Art
An SRAM(Static Random Access Memory) cell, also referred to as a flip-flop, is composed of a pair of cross-coupled inverters. That is, the memory cell's logic state is determined by a voltage level of each a pair of inverter output nodes, and when an inverter output node to which a supply voltage is applied is at a low voltage level, the other inverter output node maintains a high voltage level. Once the memory cell becomes stabilized, the stable state is maintained, so that a SRAM cell does not require a periodic refresh operation for having data stored therein, and such a characteristic of the SRAM cell is distinguishable from a DRAM (Dynamic Random Access Memory) cell. As a result, an SRAM cell is more stably operated than a DRAM cell, with a less power consumption. Also, due to self-restoring, peripheral circuits characteristics, the SRAM cell is operated in a faster mode, compared to other kinds of semiconductor memory cells.
However, it is known a disadvantage of the SRAM cell that the SRAM cell requires at least 6 transistors for forming a single cell of the kind and accordingly exhibits a lower integration factor. To solve the above-described disadvantage, there has been proposed a high-resistance load cell for 1 Mbit SRAMs by taking advantage of a polysilicon resistor, which permits a smaller region to be occupied by a memory, cell. Here, because the SRAM cell is provided with a four-transistor set and a polysilicon resistor, it is advantageous compared to a six-transistor SRAM in terms of the chip region occupied thereby. However, in a greater than 4 Mbit SRAM, a six-transistor TFT (Thin Film Transistor) SRAM cell is widely adopted mainly due to a cell data retention stability and reduced current consumption, even though the TFT SRAM cell is composed of a six-transistor set, and further TFT SRAM cell occupies a larger region than a high-resistance load SRAM cell which employs a polysilicon resistor.
With reference to
FIG. 1
, an equivalent circuit of a conventional SRAM cell is provided with a pair of NMOS access transistors Ta
1
, Ta
2
, a pair of NMOS drive transistors Td
1
, Td
2
, and a pair of PMOS load transistors Tl
1
, Tl
2
, wherein the access transistors Ta
1
, Ta
2
will be referred to as a first and second access transistors, the drive transistors Td
1
, Td
2
will be respectively referred to as the first and second drive transistors, and the load transistors Tl
1
, Tl
2
will be respectively referred to as first and second load transistors or first and second load resistors.
The gates of the first and second access transistors Ta
1
, Ta
2
are respectively connected to a word line. One end of the channel of the first access transistor Ta
1
is connected to a bit line BL, and node A connected to the other end of the channel of the first access transistor Ta
1
is connected in common to the gate of the second load transistor Tl
2
and the gate of the second drive transistor Td
2
. One end of the channel of the second access transistor Ta
2
is connected to a complementary bar bit line /BL, and node B of the second access transistor Ta
2
is connected in common to the gate of the first load transistor Tl
1
and the gate of the first drive transistor Td
1
. The source region of each of the first and second load transistors Tl
1
, Tl
2
is connected in common to high level supply voltage Vdd, and the source region of each of the first and second drive transistors Td
1
, Td
2
is connected in common to ground voltage Vss.
The operation of the thusly-constituted SRAM cell will now be described.
First, referring to a write operation of the SRAM, in order to write a data “1” in an SRAM cell, when a word line voltage is raised to a level of supply voltage Vdd so as to turn on the first and second access transistors Ta
1
, Ta
2
, the high level supply voltage Vdd is applied to the bit line BL, and the low level ground voltage Vss is applied to the bar bit line /BL, then the voltage at node A becomes a value of Vdd-Vth, whereby the second drive transistor Td
2
is turned on and the second load transistor Tl
2
is turned off. The voltage at node B becomes practically 0V, so that the first load transistor Tl
1
becomes turned on and the first drive transistor Td
1
is turned off, whereby data “1” is transferred to the SRAM cell. So long as current is continuously supplied after a data voltage of the SRAM cell is determined, the first load transistor Tl
1
remains turned on so that the supply voltage Vdd is applied via the first load transistor Tl
1
to the node A, and the second drive transistor Td
2
remains turned on so that the current of node B flows through the second drive. transistor Td
2
to ground Vss, whereby node A is turned to a high level and node B is turned to a low level so as to maintain the stored data. The steps contrary to those for a data “1” are taken for a data “0”. That is, the low-level voltage Vss is applied to the bit line BL, and the high level voltage Vdd is applied to the bar bit line /BL, so that the node A maintains a low level and the node B maintains a high level.
A read operation will now be described. Assuming that a data “1” is written into the SRAM cell, node A is a high level and node B is a low level. The respective charges of bit line pair BL, /BL for reading data are set at about 3V which is an operation point of a sense amplifier in order equalize the bit line pair BL, /BL with regard to voltage. The word line voltage is raised to the level of supply voltage Vdd, and the first and second access transistors Ta
1
, Ta
2
are turned on so as to select the target SRAM cell for carrying out a reading operation. Then, the voltage of the bit line BL is slightly raised toward the level of Vdd due to the current which flows in through the first load transistor Tl
1
, and the voltage of the bar bit line /BL flows to ground Vss and is slightly lowered, accordingly. At this time, the potential difference between the bit line BL and the bar bit line /BL is amplified in the sense amplifier (not shown) and transferred to an output buffer (not shown). Here, the reading of the data “0” follows steps identical to those for a data “1”, wherein the voltage fluctuation of the bit line BL and the bar bit line /BL is reversed compared to the case of a data “1”.
Meanwhile, in a TFT SRAM serving as one of the thusly operated SRAM kinds wherein the objective of such TFT SRAM is to increase the integration degree, the first and second drive transistors Td
1
, Td
2
and the first and second access transistors Ta
1
, Ta
2
are respectively formed of a bulk transistor, and because the first and second load transistors Tl
1
, Tl
2
are respectively provided with a structure in which the transistors Tl
1
, Tl
2
are sequentially stacked on the first and second drive transistors Td
1
, Td
2
, the TFT SRAM becomes advantageous in that it requires less chip region than a general SRAM.
With reference to
FIG. 2
illustrating a plan layout view of a conventional TFT SRAM and to
FIGS. 3A-3G
showing fabrication sequence cross-sectional views thereof, the structure of the TFT SRAM will now be described.
As shown therein, on a semiconductor substrate
1
there is formed a device isolation region
2
a
. On the region of the substrate
1
other than the device isolation region
2
a
are formed the first and second access transistors Ta
1
, Ta
2
and the first and second drive transistors Td
1
, Td
2
. That is, on the semiconductor substrate
1
are respectively formed gate electrodes
5
a
1
,
5
a
2
of the first and second access transistors Ta
1
, Ta
2
. In the semiconductor substrate
1
and on each side of the gate electrodes
5
a
1
,
5
a
2
of the first and second access transistors Ta
1
, Ta
2
there are formed the source region regions
3
a
1
,
3
a
2
and drain regions
4
a
1
,
4
a
2
, wherein the first access transistor Ta
1
includes gate electrode
5
a
1
, source region
3
a

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