Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-13
2004-05-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S254000, C438S396000, C438S397000, C438S398000, C257S303000, C257S306000, C257S309000
Reexamination Certificate
active
06730563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly, to a method of manufacturing a semiconductor device including a capacitor.
2. Description of the Background Art
One of semiconductor memory devices includes a dynamic random-access memory (hereinafter referred to as “DRAM”). As semiconductor memory devices have reduced in size, a cylindrical capacitor has been employed in the DRAM for securing a capacitance of the capacitor storing electrical charge as information.
An example of a method of manufacturing a DRAM including such a cylindrical capacitor will be described. First, as shown in
FIG. 29
, a semiconductor substrate
102
is divided into a memory cell region M and a peripheral circuit region P. A memory cell is formed in memory cell region M, whereas a circuit for controlling the memory cell is formed in peripheral circuit region P.
A prescribed memory cell transistor (not shown) is formed on a portion of semiconductor substrate
102
in memory cell region M. A silicon oxide film
104
is formed on semiconductor substrate
102
so as to cover the memory cell transistor.
Prescribed bit lines
107
a
,
107
b
are formed on silicon oxide film
104
. A silicon oxide film
106
is further formed on silicon oxide film
104
so as to cover bit lines
107
a
,
107
b.
Next, prescribed storage node contact holes
105
a
,
105
b
are formed at silicon oxide films
104
,
106
. Plugs
103
a
,
103
b
of e.g. a polysilicon film are formed in storage node contact holes
105
a
,
105
b
, respectively.
Subsequently, an interlayer film
108
is formed on silicon oxide film
106
. At interlayer film
108
, openings
108
a
,
108
b
that expose plugs
103
a
,
103
b
, respectively, are formed. A capacitor will be formed in each of openings
108
a
,
108
b.
Next, as shown in
FIG. 30
, a prescribed rough polysilicon film
110
is formed on interlayer film
108
and on the inner surfaces of openings
108
a
,
108
b
. Thereafter, as shown in
FIG. 31
, photoresists
119
a
,
119
b
are formed on rough polysilicon film
110
such that they are embedded in openings
108
a
,
108
b.
The entire surface of exposed rough polysilicon film
110
is etched by e.g. electron beam (EB) using photoresists
119
a
,
119
b
as a mask, to remove rough polysilicon film
110
positioned on the upper surface of interlayer film
108
.
Subsequently, photoresists
119
a
,
119
b
are removed. In addition, as shown in
FIG. 32
, interlayer film
108
is removed by e.g. a wet etching technique, so that cylindrical storage nodes
110
a
,
110
b
are formed.
Next, as shown in
FIG. 33
, a capacitor dielectric film
113
is formed covering storage nodes
110
a
,
110
b
. A cell plate
114
made of e.g. a polysilicon film is formed on capacitor dielectric film
113
. Storage node
110
a
or
110
b
, capacitor dielectric film
113
and cell plate
114
constitute a capacitor C.
Next, as shown in
FIG. 34
, an interlayer insulation film
115
is formed on silicon oxide film
106
so as to cover capacitor C. At interlayer insulation film
115
, a contact hole
115
a
that exposes cell plate
114
and contact hole
115
b
that exposes bit line
107
b
are formed.
A prescribed plug (not shown) is formed in each of contact holes
115
a
,
115
b
. A prescribed interconnection (not shown) electrically connected to the plug is formed on interlayer insulation film
115
. Thus, a DRAM is completed.
The conventional DRAM, however, had the following problems. As described above, in the conventional DRAM, when storage nodes
110
a
,
110
b
each forming capacitor C are formed, interlayer film
108
is removed by wet etching, as shown in FIG.
32
. Here, interlayer film
108
that lies in peripheral circuit region P is also removed.
Subsequently, as shown in
FIG. 34
, capacitor C is formed in memory cell region M, followed by interlayer insulation film
115
being formed while interlayer film
108
arranged in peripheral circuit region P has been removed.
Here, interlayer insulation film
115
covering capacitor C produces a relatively large step between memory cell region M and peripheral circuit region P. Such a step produced at interlayer insulation film
115
may deteriorate the accuracy of photolithography in forming e.g. contact holes
115
a
,
115
b
, which sometimes toughen control of the shape of openings.
Moreover, capacitor C is required to be taller in order to secure the capacitance of capacitor C, as DRAMs have been reduced in size. As the height of capacitor C increases, capacitor C including storage nodes
110
a
,
110
b
easily falls on silicon oxide film
106
at and after the process step shown in FIG.
32
.
If capacitor C falls, electrical short circuit between memory cells (between bits) is induced, lowering the product yield.
Furthermore, when rough polysilicon film
110
positioned on the upper surface of the interlayer film
108
is removed, photoresists
119
a
,
119
b
are formed such that they are embedded in openings
108
a
,
108
b
as shown in
FIG. 31
, in order to protect rough polysilicon film
110
arranged within openings
108
a
,
108
b.
Such a method, however, causes a problem in that an additional step is required for removing photoresists
119
a
,
119
b
embedded in openings
108
a
,
108
b
in addition to removal of interlayer film
108
. Moreover, when the rough polysilicon film is removed, polysilicon grains in the rough polysilicon film are sputtered.
SUMMARY OF THE INVENTION
The present invention was made to solve the problems above, and an object thereof is to provide a method of manufacturing a semiconductor device that solves the problems of the steps, falling and the like in the semiconductor device including the capacitor element as described above.
A method of manufacturing a semiconductor device according to the present invention includes the following steps. A first element-forming region and a second element-forming region are formed on a main surface of a semiconductor substrate. A first insulation film is formed in the first element-forming region and the second element-forming region. A prescribed opening for forming a capacitor element is formed at a portion of the first insulation film located on the first element-forming region, while an annular groove continuously surrounding the first element-forming region is formed. A layer that is to be a first electrode of the capacitor element is formed on the first insulation film and on inner surfaces of the opening. A protection film for protecting the layer to be the first electrode located within the opening is formed in the opening. The layer to be the first electrode located on an upper surface of the first insulation film is removed, so that the first electrode is formed in the opening. A mask material that exposes the protection film and the portion of the first insulation film located in the first element-forming region and covers the annular groove and a portion of the first insulation film located in the second element-forming region is formed to remove at least a part of the first insulation film. The protection film is removed. A second electrode is formed on the first electrode from which the protection film is removed, with a dielectric film interposed in between, to form a capacitor element. A second insulation film is formed on the semiconductor substrate so as to cover the capacitor element. The step of forming the first electrode is performed by polishing.
According to the present method, the layer that is to be the first electrode located on the upper surface of the first insulation film is removed by polishing, so that the layer to be the first electrode can be prevented from being sputtered, compared to that removed by e.g. electron beam. In addition, the first insulation film located in the second element-forming region is left by the mask material at removal of a part of the first insulation film in the first element-forming region, allowing large reduction of a step produced between a portion of the s
Kennedy Jennifer M.
McDermott & Will & Emery
Niebling John F.
Renesas Technology Corp.
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