Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-06-04
2004-03-09
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000, C438S700000, C438S723000, C438S725000
Reexamination Certificate
active
06703311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for estimating capacitance of deep trench capacitors. In particular, the present invention relates to a method of estimating capacitance before finishing the capacitors.
2. Description of the Related Art
DRAM is capable of read and write operations. Unlike other types of memory, each DRAM cell needs only one transistor and one capacitor, therefore it is easy to achieve high integration and wide use in computers and electric equipment. The trench capacitor is a commonly used capacitor, formed in the substrate. The capacitance of the trench capacitor is usually increased by increasing the depth of the trench capacitor.
The trench capacitor memory chip can be separated into a memory cell array area and a support area. The memory cell array area is used to store data, and the support area places some logic circuit and some decoupling capacitors to filter noise.
After forming the capacitors, a wafer acceptance test (WAT) is used to measure the capacitance of the formed deep trench capacitor. Further, after finishing second layer of interconnection, a deep trench short loop (DTSL) is used to test the capacitance, open circuit and leakage of the capacitors. However, these two ways cannot monitor the capacitance before forming the capacitor. If the capacitance is below standard value and detected after DTSL test, the wafer cannot recover and must be discarded.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method for estimating capacitance of deep trench capacitors before finishing the capacitors.
To achieve the above-mentioned object, a method for estimating capacitance of deep trench capacitor in a substrate is provided. The substrate includes a memory cell array area and a supporting area. A plurality of trenches is formed in the memory cell array area. A conformal oxide layer is formed in the substrate, wherein the conformal oxide layer is doped with a first conducting type dopant. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to be formed in the trenches.
REFERENCES:
patent: 5405800 (1995-04-01), Ogawa et al.
patent: 5729043 (1998-03-01), Shepard
patent: 6010933 (2000-01-01), Cherng
patent: 6031289 (2000-02-01), Fulford et al.
patent: 6281068 (2001-08-01), Coronel et al.
patent: 6353253 (2002-03-01), Hause et al.
Chuang Ying Huan
Lee Yu-Pi
Mao Hui Min
Tsai Tzu-Ching
Ladas & Parry
Nänaya Technology Corporation
Norton Nadine G.
Tran Binh X.
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