Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-11-13
2004-09-21
Gurley, Lynne A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S693000
Reexamination Certificate
active
06794285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a slurry for CMP and a method for manufacturing a semiconductor device. In particular, the present invention relates to a slurry for CMP which can be employed in the formation of a damascene wiring employed for mounting a high-speed logic LSI, a system LSI, a memory/logic hybrid LSI, etc., and to the method for manufacturing a semiconductor device.
2. Description of the Related Art
Recent years, concomitant with the advancements in the integration of LSI, the wiring pattern is now increasingly miniaturized at a high speed. In particular, in the wiring of the next generation, where the design rule is 0.1 &mgr;m or less, it is considered imperative to develop new materials to prevent RC delay of wirings. Accordingly, it is now studied to employ low resistive Cu (p: 1.8 &mgr;&OHgr;cm) as a wiring material and to employ a low dielectric constant (k:<2.5) insulating film as an insulating material.
The Cu wiring is mainly employed by forming it as a damascene wiring by using CMP (Chemical Mechanical Polishing). When the polishing of the Cu wiring is performed by CMP, a conductive material existing between wirings can be effectively removed, thus making it possible to obtain a wiring which is less likely to cause short-circuit, as compared with the wiring formed by RIE, such as the conventional Al wirings. Therefore, CMP is considered advantageous in the process of forming fine wirings.
On the occasion of forming the Cu damascene wiring by using the aforementioned CMP process, it is required that the method be capable of providing the wiring with various properties, such as excellent surface planarity, high polishing rate, low density in surface defects, low density in residual impurities and sufficient resistance to film peeling. If an organic insulating film (Low-k film) of low dielectric constant is employed as an interlayer insulating film, it would be possible to secure a high polishing rate. However, the employment of the organic insulating film would be encountered with many difficulties, as compared with the case where the conventional inorganic SiO
2
film is employed in realizing all of the aforementioned properties except the high polishing rate.
In particular, with respect to the surface planarity, the loss of the Low-k film (erosion) due to the employment of CMP would become serious. The main reason of this may be attributed to the fact that the mechanical strength of the organic Low-k film is much poorer as compared with the inorganic SiO
2
film. Furthermore, since most of the Low-k films contain organic components, the surface thereof is hydrophobic, which means that the hydrophobic surface is poor in compatibility with hydrophilic abrasive grains, thus resulting in the generation of non-uniformity in density of abrasive grains within a wiring pattern.
With a view to perform the polishing of wiring without causing damage to the Low-k film while maintaining a sufficient degree of polishing rate, there has been proposed to employ a slurry containing a fluorine-based surfactant. However, the fluorine-based surfactant is rather expensive and moreover may impose various burdens on the environment, thus rendering the fluorine-based surfactant inconvenient in its handling.
Further, due to the following reasons, it is difficult to sufficiently minimize the density of residual impurities on the surface of the Low-k film.
It is unavoidable to remain undesirable substances such as dusts (abrasive grains and cut pieces) and unreacted slurry on the surface of insulating film and wirings after the treatment using CMP. In the conventional method, these undesirable substances were removed by using a washing solution containing an organic acid or a surfactant. However, as the intervals between wirings are increasingly narrowed these days, such a washing method is no longer useful in removing these undesirable substances. Moreover, since the intervals between wirings demanded in the wirings of the next generation is as fine as 0.1 &mgr;m or less, a small amount of such a very small residual substances that have been disregarded in the prior art as not raising any substantial problem may now become a cause for the generation of wiring defects, such as short circuit between wirings, and the deterioration in voltage resistance of the insulating film.
Additionally, as described above, the surface of the Low-k film is hydrophobic and hence poor in compatibility to water. Therefore, dust is more likely to be adsorbed onto the surface of the insulating film during the treatment thereof using the CMP or during the washing treatment thereof. Moreover, since the dust adsorbed onto the insulating film cannot be removed, it may become a main cause for preventing the formation of wirings which are electrically isolated from each other normally. Furthermore, the Low-k film is accompanied with the drawback that it is vulnerable to scratches.
Additionally, since the Low-k film is inherently poor in adhesive strength, it is impossible in the employment of the Low-k film to secure a sufficiently high degree of resistance to the film peeling, thus making it one of the important and difficult problems that has to be coped with in the integration of Cu/Low-k film.
BRIEF SUMMARY OF THE INVENTION
A CMP slurry according to one embodiment of the present invention comprises:
a solvent;
abrasive grains; and
a silicone-based surfactant having an HLB value ranging from 7 to 20.
A method of manufacturing a semiconductor device according to one embodiment of present invention comprises:
forming an insulating film above a semiconductor substrate;
forming a recessed portion in the insulating film;
depositing a conductive material inside the recessed portion and on the insulating film to form a conductive layer; and
removing the conductive material deposited on the insulating film by CMP using a CMP slurry to expose the insulating film, the CMP slurry comprising a solvent, abrasive grains and a silicone-based surfactant having an HLB value ranging from 7 to 20.
A method of manufacturing a semiconductor device according to another embodiment of present invention comprises:
forming an insulating film above a semiconductor substrate;
forming a recessed portion in the insulating film;
depositing a conductive material inside the recessed portion and on the surface of the insulating film to form a conductive layer;
removing the conductive material deposited on the insulating film to expose the insulating film while selectively leaving the insulating film deposited inside the recessed portion, thereby forming a buried wiring layer; and
treating surfaces of the buried wiring layer and of the insulating film by using a treating solution comprising a silicone-based surfactant having an HLB value ranging from 7 to 20 and dissolved in water.
REFERENCES:
patent: 6270393 (2001-08-01), Kubota et al.
patent: 1 167 482 (2002-01-01), None
patent: 2002-012854 (2002-01-01), None
patent: 2002-158194 (2002-05-01), None
Matsui Yukiteru
Minamihaba Gaku
Yano Hiroyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Gurley Lynne A.
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