DRAM device

Details DRAM device DRAM device

2002-07-30

2004-05-04

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000, C438S257000, C438S637000, C438S672000

Reexamination Certificate

active

06730975

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) device and method of manufacturing the same. More particularly, the present invention relates to a dynamic random access memory (DRAM) device and method of manufacturing the same, which can prevent problems associated with an increase in depth of metal contacts in forming thereof.
2. Description of the Related Art
As the elements incorporated into a semiconductor device are integrated to a higher degree, various attempts to form a plurality of wires or the elements in a small or narrow area in a substrate have been made. It is typical of these attempts to have the semiconductor device to become more multi-layered. Particularly, a method of forming capacitors on bit line (COB) to increase surface area thereof is widely used. In this method, metal oxide semiconductor (MOS) transistors are formed on the substrate and the capacitors connected with drains of the MOS transistors are disposed on the bit lines which supply data signals to sources of the MOS transistors. Thus, required plane area in the method can be reduced as compared with a structure having capacitors formed on the substrate.
Also, to form storage electrodes of the capacitors having a large surface area in a small substrate area, hemispherical grains (HSG) can be formed on the surface of the silicon storage electrodes. However, in this case, as the semiconductor device is highly integrated, short circuit between the adjacent storage electrodes may occur. Accordingly, in a highly integrated DRAM device, a method of adopting cylindrical shaped storage electrodes and increasing height thereof is frequently used. To increase performance of the DRAM device within the limit of a certain area, an increase in the height of the cylindrical shaped storage electrodes to several &mgr;m is required. In addition, the depth of metal contacts which connect circuits within the substrate at a peripheral/core area of the DRAM device needs to be increased.
If the depth of the metal contacts is increased, according to need, silicon nitride layers have to be etched to form the metal contacts. Since it is difficult to form metal contacts having different depths in particular places, the metal contacts are prone to form short circuits with adjacent or surrounding elements. Also, since it is difficult to control the depth of the contacts, a problem may occur that the contacts are not extended enough to be connected to the required places.
FIG.
1
and
FIG. 2
illustrate cross-sectional views showing portions of a cell and a peripheral/core areas of a conventional DRAM device, respectively.
FIG. 1
illustrates the portion of the cell area taken parallel to gate lines and
FIG. 2
illustrates problems that can occur in the peripheral/core area of the conventional DRAM device in forming of metal contacts.
Referring now to FIG.
1
and
FIG. 2
, an isolation layer (not shown) is formed on a semiconductor substrate
10
to define an active region. Then, a gate insulating layer is formed on the whole surface of the substrate
10
including the isolation layer by using thermal oxidation. On the gate insulating layer, a gate layer and a capping-insulating layer are formed in order. The gate layer is formed of a polysilicon layer and a metal silicide layer, whereas the capping-insulating layer is formed of a silicon nitride layer. Then, the capping-insulating layer and the conductive layer are sequentially patterned to form a gate pattern
11
including gate electrodes and wires. Thereafter, a low concentration ion implantation is carried out on the substrate
10
. After spacers are formed on side walls of the gate pattern
11
, a high concentration ion implantation is carried out on the substrate
10
. As a result, transistors are formed to have channels and source/drain regions having dual doped structures. Over the whole surface of the substrate
10
on which the transistors are formed, a first interlayer insulating layer
15
is deposited and planarized. The first interlayer insulating layer
15
in the active region is etched to form self-aligned contact pad holes, and a conductive layer of material such as polysilicon is deposited over the substrate to fill the self-aligned contact holes. Then, the conductive layer and the first interlayer insulating layer
15
are etched by means of a chemical-mechanical planarization (CMP) process to form bit line contact pads (not shown) and storage contact pads
13
in the self-aligned contact holes.
Thereafter, a second interlayer insulating layer
17
is formed over the substrate on which the contact pads are formed. The second interlayer insulating layer
17
is patterned to form bit line contact holes
18
(not shown in the cell area of FIG.
1
). At this time, in the peripheral/core area, the bit line contact holes
18
are formed at places where a bit line pattern is to be connected to the substrate, as shown in FIG.
2
. Then, a barrier metal layer
19
′ is thinly formed over the whole surface of the substrate on which the bit line contact holes are formed. Next, a conductive layer
20
of material such as tungsten is formed on the barrier metal layer
19
′ to form bit line contacts or contact plugs. Thereafter, a barrier metal layer
19
, a conductive layer
21
of material such as polysilicon, and a silicon nitride protecting layer
23
are continuously formed and patterned to form the bit line pattern, as shown in FIG.
2
. Alternatively, after the bit line contact holes
18
are formed, the conductive layer
21
and the silicon nitride protecting layer
23
can be continuously formed without forming of the barrier metal layer
19
′ and the conductive layer
20
, and patterned to form the bit line pattern and the bit line contacts. On side walls of the bit line pattern, bit line spacers
25
which are composed of a silicon nitride layer are formed. The protecting layer
23
and the bit line spacers
25
function to prevent bridges between storage contact plugs and bit lines from being occurred when the storage contact plugs are formed. Thus, the bit lines having the spacers are formed. At this time, the portions of the bit line pattern having enlarged widths as described above forms bit lines having enlarged width portions at a portion of the peripheral/core area, to connect the bit lines with upper layered circuit wiring through metal contact plugs which are to be formed later.
Once the bit lines having the spacers are formed, a third interlayer insulating layer
27
is formed over the whole surface of the substrate and a planarization process is carried out to the third interlayer insulating layer
27
. On the third interlayer insulating layer
27
, a silicon nitride layer which acts generally as an etch stop layer
29
is formed. Then, the third interlayer insulating layer
27
and the etch stop layer
29
are patterned to form storage contact holes exposing the storage contact pads
13
. And then, a conductive polysilicon layer is deposited and planarized to form storage contact plugs
31
filling the storage contact holes. Thereafter, cylindrical shaped storage electrodes
33
which are connected with the contact plugs
31
are formed and a dielectric layer
35
is thinly deposited. On the dielectric layer
35
, a conductive polysilicon layer is formed and patterned to form plate electrodes
37
. After a fourth interlayer insulating layer
39
is formed over the whole surface of the substrate over which the plate electrodes
37
are formed, metal contact holes are formed. A conductive layer of metal material such as CVD tungsten is deposited over the whole surface of the substrate over which the metal contact holes are formed, and planarized to form metal contact plugs
41
.
At this time, when the metal contact holes are formed, there is a need to expose a portion of the plate electrodes
37
or the bit lines. Also, at a portion of the peripheral/core area, the surface of the substrate has to be exposed. Namely, the depth of the metal contact plugs

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