Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-13
2004-04-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S301000, C438S305000, C438S592000, C438S595000, C438S655000, C438S683000, C438S230000, C438S514000
Reexamination Certificate
active
06723609
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of forming a metal-oxide semiconductor (MOS) transistor on a substrate, and more specifically, to a method of forming a MOS transistor with a step source/drain extension to reduce leakage current caused by a self-aligned silicide (salicide) process.
2. Description of the Prior Art
Metal oxide semiconductor (MOS) transistors are in wide use in many electric devices. A MOS transistor has four terminals: the source, the drain, the gate, and the substrate. When a gate voltage greater than a threshold voltage of a MOS transistor is applied to the gate, a channel forms between the source and the drain due to strong inversion. Consequently, the electrical performance of the gate is an important issue in the semiconductor industry.
Please refer to
FIG. 1
of a schematic view of a MOS transistor according to the prior art. As shown in
FIG. 1
, a MOS transistor
10
comprises a substrate
12
, a gate oxide layer
14
located on the substrate
12
, a gate
16
located on the gate oxide layer
14
, a lightly doped drain (LDD)
24
either in portions of the substrate
12
adjacent to either side of the gate
16
, a pair of spacers
20
positioned on both sides of the gate
16
, and a source/drain
18
a
/
18
b
formed in portions of the substrate
12
adjacent to either side of the spacer
20
. In addition, contact plugs (not shown), which are located upon the gate
16
, the source
18
a
, and the drain
18
b
, electrically connect the MOS transistor
10
and any other metal conductors (not shown). In general, a suicide layer
22
is formed on the gate
16
, the source
18
a
and the drain
18
b
in order to reduce the contact resistance of each silicon surface. Then, contact plugs are formed on the silicide layer
22
.
The LDD
24
has a high resistivity and is thus replaced by an ultra shallow junction (USJ, not shown in
FIG. 1
) as the manufacturing line width is less than 0.18 microns. Due to an increase in the complexity of integrated circuits, sizes of MOS transistors are reduced to increase the amounts of MOS transistors per unit area. However, the shallower the junction depth of the ultra shallow junction, the smaller the distance between a bottom of the source
18
a
/drain
18
b
and a bottom of the silicide layer
22
. As a result, shrinking the sizes of MOS transistors causes the diffusion of metal atoms in the silicide layer
22
into the substrate
12
and increases the leakage current of the MOS transistor
10
. In addition, as the width of the gate
16
reduced due to the reduction of the size of the MOS transistor
10
, the correspondingly decreased distance between the two ultra shallow junctions on opposite sides of the gate
16
frequently lead to a punch through phenomenon of the MOS transistor
10
. The performance of the MOS transistor
10
is therefore reduced.
SUMMARY OF INVENTION
It is therefore a primary object of the present invention to provide a method of fabricating a metal-oxide semiconductor (MOS) transistor.
It is another object of the present invention to provide a method of preventing the leakage current in an ultra shallow junction of a source/drain extension of the MOS transistor.
According to the claimed invention, a gate oxide layer and a gate are sequentially formed on a silicon substrate. By performing a first ion implantation process, the source/drain extension is formed in the silicon substrate. A liner layer is then formed to cover the silicon substrate, and a dielectric layer and a sacrificial layer are sequentially formed on the liner layer thereafter. By performing a first etching process, an arc-shaped spacer is formed on either side of the gate, and portions of the dielectric layer and the sacrificial layer atop the gate are removed. A L-shaped spacer is then formed on either side of the gate by performing a second etching process to remove portions of the sacrificial layer within the arc-shaped spacer. By performing a third etching process, portions of the liner layer not covered by the L-shaped spacer are removed. By performing a second ion implantation process, a step source/drain extension and a source/drain are simultaneously formed in the silicon substrate, wherein the source/drain extension, the step source/drain extension and the source/drain are in a gradient profile. Finally, a self-aligned silicide (salicide) process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.
It is an advantage of the present invention against the prior art that a plurality of ion implantation processes is performed to form the source/drain extension, the step source/drain extension and the source/drain in the gradient profile, increasing the distance between a bottom of the source/drain and a bottom of the silicide layer. The leakage current in the ultra shallow junction of the source/drain extension of the MOS transistor is thus prevented. In addition, a punch through phenomenon of the MOS transistor as described in the prior art is prevented as well. Therefore, as sizes of MOS transistors are reduced to increase the amounts of MOS transistors per unit area due to an increase in the complexity of integrated circuits, the method of fabricating the MOS transistor provided in the present invention can assure the performance of the MOS transistor, making the product more competitive.
REFERENCES:
patent: 5153145 (1992-10-01), Lee et al.
patent: 6297132 (2001-10-01), Zhang et al.
patent: 6380039 (2002-04-01), Badenes et al.
patent: 6432784 (2002-08-01), Yu
patent: 6506650 (2003-01-01), Yu
Chien Chin-Cheng
Kao Chia-Hung
Yang Ming-Sheng
Hsu Winston
Niebling John F.
Pompey Ron
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