Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-08-03
2004-07-13
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S503000, C375S376000
Reexamination Certificate
active
06763474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved method for system synchronization and in particular to an apparatus and a method for adjusting the time of day clocks in a heterogeneous computer system. Still more particularly, the present invention provides an apparatus and a method for high resolution frequency adjustment for node synchronization that can be used in a non-uniform memory access (NUMA) computer system.
2. Description of the Related Art
A phase locked loop (PLL) is a very interesting integrated circuit that blends analog and digital techniques. Although the basic design of a PLL has been known for decades, the circuit only became a practical building block in integrated circuit form where the cost has become affordable and the design has become more reliable.
The PLL contains a phase detector, an amplifier, a voltage controlled oscillator (VCO), and a feedback loop that allows the output frequency to be a replication of the input signal with noise removed or a multiple of the frequency of the input signal. PLLs have been used for demodulation of FM signals, for tone decoding, for frequency generation, for generation of “clean” signals, and for pulse synchronization, to name but a few of the applications. Because the output frequency is a multiple of the input frequency, it is difficult to make fine frequency adjustments using such a frequency synthesizer.
A non-uniform memory access (NUMA) computer system is a multiple processor architecture where there is a single memory address space but where memory is separated into “close” banks of memory and “distant” banks of memory. Access is “non-uniform” because the access times for the close banks of memory directly associated with the node that contains the CPU are much faster than the access times for distant memory banks at other nodes in the system. A distinct advantage of a NUMA architecture is that it scales well, in the sense that adding more nodes and processors to the system does not create bottlenecks that degrade performance in the same way as other parallel architectures.
One problem with NUMA architectures is to keep the nodes synchronized. Transactions are often labeled with time stamps that are generated by the time of day at each node in the system. Since these nodes have independent clocks, even though they are initialized at precisely the same time, they will eventually drift apart and require re-synchronization. It is important to have precise time stamps with as little “cycle slippage” as possible between the nodes.
Therefore, it would be advantageous to have a method for high resolution frequency adjustment for node synchronization that can be used in a non-uniform memory access (NUMA) computer system.
SUMMARY OF THE INVENTION
An apparatus and a method is presented for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. A non-uniform memory access (NUMA) computer system is one such system where this method and apparatus can be applied.
Transactions in a multiprocessor computer system must be coordinated precisely for correct operation. Time stamps are attached to transaction requests and when data is changed in the system, the relative values of time stamps are critically important. These time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates in the multiprocessor computer system may be lost.
This invention monitors the relative phase of a “master” time of day register with one or more “slave” time of day registers. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.
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Boerstler David William
Dean Mark Edward
Ngo Hung Cai
Zimmerman Andrew Christian
Du Thuan
Lee Thomas
Salys Casimer K.
Tkacs Stephen R.
Yee Duke W.
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