Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-26
2004-01-13
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06677774
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to an integrated circuit (IC) diagnosis technique and, more particularly, to an apparatus and a method for determining the location of an I
DDQ
defect in an integrated circuit.
Presently, there are several different types of testing methods for detecting faults in integrated circuits. However, one particular method has been widely accepted and successful in the electronics industry. This one particular method comprises a complementary metal oxide semiconductor (CMOS) integrated circuit test method which is known as quiescent power supply current, or I
DDQ
, testing.
I
DDQ
testing is attractive because it can achieve high fault coverage with relatively few test patterns, and can detect certain types of unique defects (for example, subtle transistor leakage mechanisms and highly resistive bridges) that logic and functional testing may not detect.
I
DDQ
testing is based on the observation that certain commonly occurring semiconductor defects, such as bridges or shorts between metal lines, will cause an IC to draw extra supply current, even when the IC is in a “quiescent” state in which all of its intended conduction paths are turned off. Such a defect forms an unintended conduction path between two or more electrically active regions of the IC, and extra current will result (i.e., the defect is “activated”) whenever these regions are at different electrical potentials.
Such a defect, which is detectable by an I
DDQ
test, will be referred to as an “I
DDQ
defect” hereafter. Also, the current resulting from a defect will be referred to as “I
DDQ
defect current”. It should be noted that an I
DDQ
defect may not be in close physical proximity to the sites in the power and ground networks where the additional current enters and exits the chip. The current arising from a bridge between two signal lines, for example, has its source and sink in the two circuits which drive the bridged lines, either or both of which may be far removed from the location of the actual defect. Hereinafter, for the sake of brevity, any reference to the existence of an I
DDQ
defect within a particular physical area is intended to include the possibility that the area identified contains only a circuit of which output signal line contains a defect, and that the defect itself may in fact lie outside the area identified.
A single reading is typically obtained by applying a predetermined test pattern to the primary inputs of an IC, allowing the IC to “settle” into a quiescent state, and then measuring the current drawn by the IC in the quiescent state. An I
DDQ
test normally comprises the application of several such test patterns and measurements. Each pattern places the IC into a different electrical state, thereby increasing the likelihood of activating, and thus of detecting, any I
DDQ
defects present on the IC.
A semiconductor manufacturer's ability to improve its manufacturing yield depends upon successful physical failure analysis (PFA), in which the root cause of an IC's failure is determined. Central to successful PFA is the ability to determine the physical location of a defect on an IC. Because traditional I
DDQ
testing measures current at a single point in the IC's power supply, each reading indicates the current drawn by the entire IC. For this reason, traditional I
DDQ
measurements provide no direct information about the physical location of the defects they detect. A means for determining the location of a defect directly from I
DDQ
measurements could improve the accuracy and effectiveness of PFA, enabling more rapid improvement of manufacturing yield.
In the absence of such a method, one existing means of locating an I
DDQ
defect is software diagnosis. Given a logic simulator which can determine the internal electrical state of the IC during each I
DDQ
measurement, and an indication of which I
DDQ
measurements “failed” (detected the defect) and which “passed”, I
DDQ
diagnostic software can determine likely defect sites by identifying internal circuit nodes which, if defective, could explain which patterns pass and fail.
Although test and diagnosis offer unique benefits to IC manufacturers, the effectiveness of I
DDQ
testing has been generally diminished because of its increasing difficulty of detecting I
DDQ
defect current in the presence of the overwhelmingly higher background current (e.g., substrate current). Such background current is a very typical phenomenon in modern integrated circuit devices. Even a defect-free integrated circuit draws a certain amount of background current while in a quiescent state because of a normal leakage phenomenon within individual devices (e.g., transistors) within an IC device. As the number of transistors in advanced integrated circuit devices has exponentially grown, the background current arising from their cumulative leakage has increased drastically.
Because the current resulting from an activated I
DDQ
defect is typically small, the “signal-to-noise” ratio in I
DDQ
testing (that is, the ratio of defect current to normal background current) has become so low that some IC manufacturers have abandoned I
DDQ
testing altogether as ineffective for their high-performance IC's. A means of increasing this signal-to-noise ratio would thus not only extend the applicability of I
DDQ
testing for defect detection, but would improve the capability of software diagnosis by enabling “passing” and “failing” patterns for a given IC to be distinguished more readily.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved and more accurate method for testing an integrated circuit by improving a ratio between defect current and background current within the integrated circuit.
Another object of the present invention is to provide a method for improving the ratio between defect current and background current for integrated circuit testing by dividing an integrated circuit into a plurality of areas and individually measuring an amount of I
DDQ
defect current generated in each area.
Still another object of the present invention is to provide an improved and accurate method of determining the presence of an I
DDQ
defect based on the measured amount of I
DDQ
defect current generated in each area.
Further, an object of the present invention is to provide an apparatus and a method for determining a location of an I
DDQ
defect within the integrated circuit based on the measured amount of I
DDQ
defect current generated in each area.
A further object of the present invention is to provide a method for creating an I
DDQ
current map of an integrated circuit based on the measured amount of I
DDQ
defect current generated in each area.
Additional objects and other features of the present invention will be set forth in part in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects and advantages are achieved in part by a method of testing an integrated circuit which has a plurality of terminals on a surface thereof. The surface is divided into a plurality of areas, each area is provided with at least one of said plurality of terminals. An I
DDQ
defect is activated to generate I
DDQ
defect current within the integrated circuit. Amounts of the I
DDQ
defect current transferred to said plurality of terminals are measured. Based on the amount of said I
DDQ
defect current measured at the plurality of terminals, it is determined whether each area includes said I
DDQ
defect.
Thus, by dividing an integrated circuit into a plurality of areas and measuring the I
DDQ
defect current generated within each area, the present invention significantly increases the ratio between signal (I
DDQ
defect current) and noise (e.g.,
Buffet Patrick H.
Heaberlin Douglas C.
Pastel Leah M. P.
Sun Yu H.
Cuneo Kamand
Kobert Russell M.
Walsh Robert A.
Whitham Curtis & Christofferson, P.C.
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