Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-17
2004-05-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C438S692000
Reexamination Certificate
active
06734070
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, more particularly a method of fabricating a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) in a semiconductor device.
2. Description of the Related Art
As semiconductor technology moves to increasing levels of large-scale integration and the dimensions of integrated field-effect transistors are increasingly reduced, the source and drain diffusions of the transistors must be made increasingly shallow to avoid deleterious short-channel effects. For PMOSFETs this presents a problem, because the boron ions implanted as an impurity to form the source and drain diffusions are small in mass and therefore penetrate comparatively deeply into the substrate during the implantation process.
One well-known solution to this problem is to reduce the boron ion implantation energy, but that also reduces the ion current, thus requiring a longer implantation time and delaying the fabrication process.
Another well-known solution is to implant boron difluoride (BF
2
) ions, which are more massive than boron ions and can be implanted with greater energy to an identical depth. Conventional fabrication processes, however, implant the same impurity into the gate electrode as into the source and drain regions, and it has been found that the presence of fluorine in the gate electrode leads to penetration of the gate oxide film by boron atoms during the subsequent drive-in process. Unwanted boron then accumulates in the channel, region below the gate electrode, greatly altering the transistor threshold voltage.
Another known solution, disclosed in Japanese Unexamined Patent Application Publication No. 2001-156289, implants boron ions into the source and drain regions and gate electrode through a dielectric film, such as a film of silicon dioxide or silicon nitride eighty to one hundred eighty nanometers thick, covering the gate oxide film and the gate electrode. This process enables boron ions to be implanted with comparatively high energy to a comparatively shallow depth in the source and drain regions, without introducing unwanted fluorine into the gate electrode.
Measurements performed by the inventor on PMOSFETs fabricated by this process have disclosed a further problem, however. Optical measurements of the gate oxide film thickness disagree with electrical measurements of the gate capacitance, implying the existence of an unwanted parasitic capacitance in series with the capacitance due to the gate oxide film. The explanation for the discrepancy is thought to be that the shallowness of the source and drain diffusions is mirrored by a shallowness of the boron diffusion into the gate electrode leaving a depletion zone at the bottom of the gate electrode, near the gate oxide film.
FIG. 25
is a sectional view showing the substrate
2
, gate electrode
4
, gate oxide film
6
, and suspended depletion zone
8
. The effect of the depletion zone
8
is to thicken the layer of insulation between the gate electrode
4
and substrate
2
, reduce the total gate capacitance, and thus reduce the driving capability of the transistor.
The depletion zone could be eliminated by a lengthy high-temperature drive-in process, but this process would also deepen the source and drain diffusions, defeating the original purpose of the silicon dioxide or silicon nitride film, and would also tend to drive boron through the gate oxide film into the channel region.
SUMMARY OF THE INVENTION
An object of the present invention is to fabricate PMOSETs with shallow source and drain diffusions, without leaving a depletion zone in the gate electrodes.
When a field-effect transistor is fabricated according to the present invention, a gate oxide film is formed on a semiconductor substrate, a layer of a semiconductor material such as polysilicon is deposited on the gate oxide film, and a first dielectric film is formed on the layer of semiconductor material. The first dielectric film and the layer of semiconductor material are then patterned to form a gate electrode covered by a remaining part of the first dielectric film.
A second dielectric film is deposited to form sidewalls on the gate electrode and the remaining part of the first dielectric film, and a first impurity is implanted into the substrate through the gate oxide film to form source and drain regions.
A third dielectric film is now formed. The third dielectric film masks at least those part of the source and drain regions adjacent the gate electrode, while exposing the remaining part of the first dielectric film. The third dielectric film may be formed by, for example, oxidation of the surface of the substrate, chemical vapor deposition followed by patterning, or chemical vapor deposition followed by planarization or etch-back.
The remaining part of the first dielectric film is then removed by etching, and a second impurity is implanted into the gate electrode.
Boron difluoride may be implanted as the first impurity and boron as the second impurity.
A third impurity such as boron or boron difluoride may be implanted before the formation of the sidewalls, to create a lightly doped drain.
By implanting the first and second impurities separately, the invention enables the implanting conditions for the source and drain regions and the implanting conditions for the gate electrode to be optimized separately. The second impurity can thus be implanted to an adequate depth in the gate electrode while the first impurity is implanted to a shallow depth in the source and drain regions.
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patent: 07-122746 (1995-05-01), None
patent: 2001-156289 (2001-06-01), None
Lindsay Jr. Walter L.
Niebling John F.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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